I got a favorite new tool at Black Mesa. A saw blade for an Xacto knife I rarely used previously. For a $5 blade pack I can now make custom connectors any dimension I need. Saves me a ton of $ as I can purchase a single 1×40 0.100 from Jameco for $1 and cut it up into multiple smaller connectors ( example below 1×6 ) that would cost be about $1 each from Digikey. Trick is to pull the pin adjacent to the last pin desired and then saw away under a microscope and cleanup with a metal file at the end. Works fantastic.
Sometimes the simplest projects are the best. This is my “Backdoor to Scope Out” project. I use my “Backdoor” connection to interface a computer to FPGAs when a regular bus ( PCI ) isn’t available. What I call the “Backdoor” is just a FTDI 1×6 asynch serial connection at 921,600 baud – pretty much standard in Arduino land – I just use it as a really slow bus bridge into FPGAs. As soon as a regular connection ( PCI for example ) is working, the backdoor connection goes unused. This project repurposes the otherwise dormant Backdoor header for debug to drive state signals out to an oscilloscope using low cost cables. The cable solution I chose was 1/8″ TRRS ( headphone jack ) to RCA Audio-Left,Audio-Right, Composite-Video that was standardized by the Camcorder industry. The cables are cheap ( $10 ) and fairly high quality that go 3′ to 6′ from a compact 1/8″ headphone plug to 3 RCAs that are easily converted to BNC.
The first board converts a 0.100″ Header to a thru-hole TRRS jack. I was shocked and disgusted to discover that “shield” isn’t used for signal return ( Ground ) on the TRRS connector – but instead used for Audio.
The second board converts the 1×6 FTDI header to the “new” 1×6 reversible scope-out header. I wanted to make the connection reversible so that the ~bulky~ 1/8″ plug and socket could go in 1of4 orientations when plugged in to guarantee clearance from other components that may be on a PCB.
The final test for the project was to drive a 50 MHz and 40 MHz square wave onto 2 of the 3 RCA cables over 6 feet and observe final signal integrity and any potential cross talk. End result was great – perfect for FPGA state debugging. Total cost for complete 3 channel solution was under $20. Now I have a robust 3 channel 0.100″ connection to an oscilloscope using readily available cables.
Sometimes convenience has a price. I designed this PCB tonight to use with my new idea of connecting a 3.5mm TRRS jack ( 3.5mm headphone ) to 3 FPGA outputs then adapt that to a readily available camcorder cable with 3 RCAs ( Red,White,Yellow ) to BNC then to oscilloscope. This board takes up to 8 of those RCAs and adapts them to a Saleae 1×9 0.100″ logic analyzer pinout instead. Simple to design, but the board was 1″x2″ due to the RCA connector size, I even shared vias between RCA connectors to save area – still $9 for a stupid interconnect adapter. Hope its useful in the long run. Idea for this board is that RCA cables are normally plugged into a analog scope for quick live measurements and can be easily switched to a Saleae for digital capture at 10 MSPS for seconds worth of sampling.
Assembled my first NanoPi FPGA board today! The NanoPi is a variation of my existing Nano6 Xilinx Spartan6 2 layer FPGA breakout board but designed specifically to connect mechanically and electrically with a RaspberryPi A+ or B+ Linux single board computer. Purpose of the project is to greatly enhance the low cost Linux SBC infrastructure provided by the Pi with fully flexible and custom real time hardware control and high speed IO of a low cost FPGA.
Connected together they make up a 32bit ARM Linux workstation with USB,Ethernet, HDMI video and a software reconfigurable FPGA providing 250K gates of logic, 512Kbits of RAM and 32 configurable LVCMOS or LVDS high speed IO. Very small package for only $50 BOM cost with tremendous amount of capabilities.
What I found most intriguing about this project is that I can configure Linux on the Pi ( Raspian , derived from Debian ) to boot and automatically login in and execute a predetermined Python script of my choosing. Python on the Pi has full access to video and GPIO ports. The Pi provides a 125 MHz SPI serial port that I have connected directly to my Nano FPGA. Now all I need to do is write the Verilog for the SPI interface to LocalBus bridge inside the FPGA and a simple Backdoor library of calls in Python for doing low level bus writes and reads to the FPGA. At 125 MHz and sending binary this FPGA Backdoor interface will be 200x faster than my Windows FTDI 921,600 baud UART interface I currently use sending ASCII. In the past, if I wanted a hardware project with any kind of low power and small form factor, I would have to turn to an ARM7 chip or Arduino and write and compile C code – a time consuming process. With this platform, I can script everything in Python ( much faster to develop in ) and initially store all the files on my Synology NAS network drive as the Pi easily mounts my filesystem thanks to Samba. Tremendous improvement in productivity over writing embedded C. The Pi can also run completely headless and the serial port can be used for remote shell login for using Vi to edit and test software.
Now for technical details of the project: The FPGA is a 45nm Xilinx Spartan6 XC6SLX9 that I buy onesie-twosie from Digikey for $15 ( probably $5-$7 in volume ). The FPGA is powered from 5V supplied either by the RaspberryPi or the FTDI header. Two diodes prevent the Pi from trying to power a computer plugged into the FTDI cable or vice versa. Two SOIC8 LDOs regulate the 5V down to 3.3V IO and 1.2V core voltages the FPGA requires. A 40 MHz reference oscillator provides a clock that the FPGA can PLL any internal core clock frequency it needs. Finally, an 8Mbit SPI PROM provides 2x the capacity needed for a single FPGA bitstream. The total BOM for the design is about $30 including misc Caps, Resistors, LEDs , Diodes and connectors. FYI – for them same price I also purchased the RaspberryPi SBC – manufactured in millions, quite the bargain. The FPGA has 2 x16 Nano Bus Connectors, a 1×6 FTDI serial port connector and dedicated traces going to the Pi’s GPIO connector for UART Serial, SPI Serial and a hand full of GPIOs. A x8 expansion connector ( currently not populated ) is shared between the Pi and the FPGA and could potentially be used for an add on board for switches, knobs, LEDs, etc.
[ Board Design ]
Board design was very straight forward. I took my 2 layer ExpressPCB design files from my original Nano6 skinny and widened the design to match the Pi’s width and allow for 2 x16 Nano bus connectors instead of the single x16 of the Nano6 skinny and routed all the signals I could from the Pi’s 2×20 GPIO connector to the FPGA’s unused pins. Board cost was $15, about 2x my normal FPGA breakout board cost for a 2 layer PCB from OSH-Park.
[ Board Bringup ]
Step-1 : Initial bringup of the FPGA board post assembly always starts out with applying 5V from my linear bench supply and making sure excess current isn’t flowing due to any solder shorts or just plain wrong design errors. Around 10mA is typical. I always visually inspect the FPGA under a microscope at 30x, so shorts usually don’t exist by the time I apply power.
Step-2 : Loading Bootloader bitstream via JTAG. The FPGA wants to configure itself on powerup from the SPI PROM, but the SPI PROM is empty initially so I use the Xilinx JTAG programmer along with Impact application on Windows to load my bootloader bitstream into the FPGA. Normally I include the Digilent HS2 JTAG footprint ( 1×6 0.100″ ) for quick JTAG access on a board. For this design I didn’t have the PCB area available around the FPGA so I instead did a 2×2 0.100″ grid with only TMS,TCK,TDI,TDO signals. GND and 3V VREF are available on the Nano x16 bus headers. I never actually solder headers into my JTAG vias as I use JTAG usually just once on bringup. Instead of solder header, I insert the header pins on the flying lead wires and apply pressure against the vias to establish a good contact during the download process. It takes two hands, but installing headers would be extra effort, extra cost and also ruin the overall appearance of the finished design. With the bitstream loaded over JTAG – if the FPGA is functioning, my 1Hz heartbeat LED will flash and I can continue to the next step of loading the PROM.
Step-3 : Loading the PROM can be done using Xilinx SW – but it doesn’t work always using an HS2 JTAG adapter, so instead I rely on my own bootloader design and BD_SHELL.exe application. My bootloader design is a simple “BSP” FPGA design that provides Backdoor LocalBus access via FTDI to a SPI PROM interface and some control registers. BD_SHELL.exe has built in command for loading SPI proms from bitfiles into multiple “slots” of a SPI PROM. The 1st Slot-0 is where my bootloader design is placed. For the XC6SLX9 FPGA, the 8Mbit PROM has room for 2 slots. My bootloader design on startup checks the logic level of an external jumper pin, if the jumper is open, the design initiates an ICAP reconfigure to Slot-1. If the jumper is closed, the bootloader design in Slot-0 stays resident, allowing the PCB to always be reconfigured over USB even if a bad user design is loaded into Slot-1. Loading the PROM takes three steps from BD_SHELL.
1) prom_root : this unlocks slot-0 which is normally locked and unable to be written to.
2) prom_load slot0.bit 0 : this loads slot0.bit into slot-0 ( the bootloader )
3) prom_load slot1.bit 1 : this loads final user design into slot-1
Once the PROM is correctly programmed, I should never have to use JTAG again ( Yes! ) as a simple jumper will guarantee the bootloader design stays resident, allowing BD_SHELL.exe to program Slot-1 of the PROM via USB FTDI interface. The Pi will also have access to the PROM interface, allowing for network FPGA firmware updates over Wifi or Ethernet. Last I checked – trying to do this from Arduino was more than just an afternoon project.
Step-4 : Board Level Test : The bootloader design has 2 purposes, 1) a guaranteed way of reconfiguring the FPGA PROM even if a bad user design is loaded and 2) provide a built in self test feature for testing that a board has been assembled correctly. Typing “prom_bist” from BD_SHELL will enable the BIST feature of the bootloader design. When BIST is enabled, the IOs of the x16 Nano bus connectors that are normally tristated will be actively driven by an 8bit counter. Board level test is performed by taking a scope probe ( or a Saleae 8bit lead ) to all the IO pins and confirming they are toggling as expected.
Whats Next? As I mentioned, I need to write a bunch of Verilog for the SPI interface to LocalBus bridge and then some Python. I have plans to have the FTDI connector to the FPGA wait for 30 seconds ( how long Linux takes to boot ) and if the FPGA’s backdoor hasn’t been opened by an external PC ( Windows running BD_SHELL ) then the FTDI connector will get redirected from the 921,600 Backdoor FPGA interface to the 115,200 RaspberryPi terminal login interface instead. This will allow a user to run the Pi headless and use a standard FTDI cable for remote login from an external PC. I supposed I could have included 2 FTDI headers, but this seems cleaner. Regarding applications – the NanoPi can be used for all sorts of stuff potentially. It provides the power and flexibility of the Python scripting language with the high speed IO capabilities and real time logic functions of an FPGA. By designing PIT timers into FPGA logic, Python scripts may be interrupted to perform time sensitive actions that usually wouldn’t be possible in a scripting environment. Potentially the NanoPi could be used for things like chip testing and board testing, running tests written in Python that interface to external hardware via the FPGA and then generating reports that are either sent off over ethernet, serial or stored locally on a USB flash drive. Its a platform with huge potential in the size of a pack of cigarettes ( do people still say that ? ).
Looking forward to the next stage of this project – writing Python and Verilog to make the combination come alive. Stay tuned!
One of my favorite tools ( that I forgot to mention when talking bout my Microscope and Oscilloscope ) is my 8bit Saleae Logic Analyzer. It is a $150 8bit LVCMOS, 24 MSPS logic analyzer that works by sampling signals using a Cypress CY7C68013A, a single chip that contains a synchronous input FIFO, 8051 uC and a USB 2.0 interface. The hardware is not all that impressive, but the software is mind blowing fantastic. It is a full waveform GUI that is easy to configure and has built in decoding for UART, SPI, I2C, etc. The most impressive feature is that the samples aren’t stored locally, but in Windows RAM and the UI makes it trivial to acquire over a billion samples over a 10 second period and rapidly navigate those billion samples visually for things like spurious interrupts, etc. It is really a great tool for capturing a tremendous amount of data and sorting through it.
Sadly, Saleae has stopped making the original low cost 8bit logic. As far as I can piece together, they had them manufactured overseas and clones of the $150 Saleae started showing up on eBay for $15. One company even brazenly uses a picture from the Saleae website showing that the Saleae software will run on their PCB. It turns out that the Saleae crown jewel ( the software ) is available for downloading and the hardware they charge $150 for has a $10 BOM and is trivial to copy. Hard lesson to learn. IBM learned it the hard way and made Microsoft very rich. Now Saleae is planning to manufacture their new products themselves – which I can’t fathom their volume being high enough to justify. Its too bad they don’t open-source their old hardware design and sell their software ( with keys ) for the clone market. As of today,you can’t buy their old products anymore and their new products have a long lead time for delivery. The Amazon and Sparkfun distribution channels are completely dry of anything from Saleae. I fear for their long term survival.
Anyways – great products, great software technology – highly recommended.
[ 01.14.2015 ] Fully evaluated my new USB 2.0 FT232H board tonight. Modified my Xilinx Spartan6 Nano FPGA design to PLL the 40 MHz reference XO to 120 MHz instead of 80 MHz so I could get a perfect UART divisor to 24 MHz for 12Mbaud communication. Then I modified my SUMP.exe application to configure the FTDI DLL for communications at 6 Mbaud and 12 Mbaud instead of normal 921,600 baud. Learning how to communicate to the FTDI DLL from Powershell ( I had to reverse engineer C# example code ) in December 2014 was what started this project to begin with as it allows configuring baud rates faster than Windows COM limits (921,600). With everything modified I had SUMP measure the event dumps of 8KB FPGA RAMs using the different physical interfaces ( USB 1.0 FT232R vs USB 2.0 FT232H ) and different software interfaces ( Windows COM driver versus FTDI DLL ). My new board is definitely faster ( 3.5x ) but not the 12x faster that I had hoped for. Would it be faster with a C or C# application instead of Powershell? Probably, I’m not about to go down that path though.
USB 1.0 FT232RL COM4 @ 921,600 baud : SUMP Dump took 248ms or 262Kbps. 1.00
USB 1.0 FT232RL DLL @ 921,600 baud : SUMP Dump took 240ms or 273Kbps. x1.04
USB 2.0 FT232H COM4 @ 921,600 baud : SUMP Dump took 257ms or 255Kbps. x0.97
USB 2.0 FT232H DLL @ 921,600 baud : SUMP Dump took 237ms or 277Kbps. x1.06
USB 2.0 FT232H DLL @ 6,000,00 baud : SUMP Dump took 83ms or 790Kbps. x3.02
USB 2.0 FT232H DLL @ 12,000,00 baud : SUMP Dump took 71ms or 923Kbps. x3.53
So, I suspect I may have hit a Windows / Powershell limit at around 900Kbps payload at 12Mbaud using the default asynchronous 2-wire interface. This probably puts a kabosh on my next board with the FT232H that has the 40MByte/sec 8bit FIFO interface ( 320Mbps theoretical ). I am skeptical I will get any faster than the 12Mbaud asynch serial and its a lot of Verilog writing and debugging to implement the FIFO interface inside the Spartan6 FPGA, not to mention consuming a full Nano x16 bus connector. I like to follow the Ethernet evolution model of not changing until you can achieve a 10x improvement. 3.5x improvement is good – but not 10x. I think I may have to make the trade off of rapid SW development in a scripting language ( Powershell ) versus fastest possible HW interface requiring low level compiled code ( C, C++ ), since SUMP transfers RLE compressed data anyways – really, I guess I’m not in THAT much of a hurry as it is transferring the entire event dataset in 250ms at 921,600 baud – which isn’t too bad really, that’s not even enough time to get a cup of coffee.
Question : FTDI just announced the new chip FT600Q that does USB 3.0 Superspeed ( 5 Gbps ) in a MLF56 package. Do I design a Nano x16 peripheral board for one when they ship end of this month? Maybe – it would be a great technical achievement to get 5Gbps SERDES chip – “Black Mesa Labs – Delivering 5Gbps SERDES on 2-layer PCBs”. Will it be faster than my new FT232H USB 2.0 ? probably not constrained by Powershell and Windows. Great challenge regardless. Wait and see I suppose…
[01.14.2015] I designed a very simple $2 circuit board to breakout a “TRRS” (Tip-Ring-Ring-Shield ) 3.5mm headphone jack that you see all over the place these days. I’m wanting to drive multiple channels of an oscilloscope and the 3 RCA to 3.5mm TRRS cables seem to be in use everywhere and would be useful for low bandwidth ( ~50MHz ) applications for capturing digital state transitions ( not so much signal integrity ). The TRRS jacks exist in smart phones to support earbud head sets with microphones and also in video devices ( video iPod, camcorder, etc ) to deliver Left and Right audio plus a Composite video on 3 conductors plus a return instead of the normal “TRS” Tip-Rings-Shield 2 conductor stereo connector. Digging into to their pinout I was astonished to find out that mechanically all the TRRS plugs and receptacles seem compatible, but electrically EVERYBODY wires them up differently. The return signal actually isn’t the “S” ( shield ) for most manufacturers ( although it is for some ). The “S” is return for 3.5mm mono, 3.5mm stereo, but not necessarily 3.5mm TRRS 3 conductor. Some devices go in the TRRS order of “Audio-Audio-Ground-Video”, some “Audio-Video-Ground-Audio”, some “Audio-Audio-Video-Ground”. I looked up various TRRS to RCA cables on Amazon and about 1/2 the reviews said things like “piece of junk – didn’t work” or “audio on only one channel, no video” or “didn’t work until I plugged the red into video and yellow into audio jack”. What a disaster. How much does this cost Amazon in returns? Bad design decisions like these are made by electrical engineers and it really makes the industry look bad. I ended up going with the “Camcorder” ~standard~ as at least multiple manufactures agreed to it for video cameras ( but of course I won’t be able to use an Apple video cable ). I found a good writeup up on this whole TRRS mess here . To think electrical engineers helped get men on the moon in 1969.
[ 01.12.2015 ] Assembled my new USB 2.0 12Mbps UART board today. Thought I would take the opportunity to blog about the entire process from start to finish – board design, procurement, surface mount assembly and final test.
[ 12.23.2014 ] Started new ExpressPCB 2-layer design for a small 1″x0.5″ board to replace a standard 1Mbps FTDI Cable but run 12x faster using a USB 2.0 chip from FTDI – the FT232H. All of my previous FTDI board designs have used the FT232R as it is a smaller chip that includes an oscillator and all the USB passives on chip. The FT232R interfaces to USB at a conservative 12 Mbps versus SERDES 480 Mbps for the FT232H. The FT232H requires a lot more support circuitry ( 12 MHz precision oscillator, protection diodes and is in a bigger package ). Expecting a 2-layer PCB to work at 480 Mbps was a huge $3 gamble I was willing to take.
[ 12.26.2014 ] Finished the design ( working on it part time – had other things going on the last few days ). Typical design flow is schematic design and then have a computer autoroute. My flow is quite different in that I manually place components where I think they can be routed using only two layers and also assembled by hand in as small area as possible. Using ExpressPCB version 7.0.2 (only), layout is done manually using a vector drawing program. Red signifies copper on the top, green copper on the bottom, yellow silkscreen on top for labeling. Designing a PCB like this is very much a challenging puzzle. After I finish the design, I import the ExpressPCB file into CopperConnection and export a single *.ZIP containing layer Gerbers and Excellon drill files in OSH-Park selected format. This process takes about 10 seconds. I could actually layout my board design in CopperConnection – but I already know ExpressPCB – so why bother learning a new tool? ExpressPCB is a great service for at work when I need a board fast. When I’m not in much of a hurry, OSH-Park is super inexpensive and high quality.
[ 12.26.2014 ] Uploaded Gerber and Excellon *.ZIP file of design to OSH-Park. The website takes a few minutes and presents a rendering of all the different layers ( Copper, Solder Mask, Silkscreen, Drill holes ). Approve and purchase the design 0.61×1.21 inch (15.39×30.66 mm) 2 layer board for $3.65
Here is an example OSH-Park panel that I found on the web that they showed at a Makerfaire in Portland in 2013. Notice how small all the designs are and how much daylight shines through. Their software does a fantastic job of panelizing multiple small gerber designs. Other low cost PCB places like IteadStudio stick with simple fixed rectangles on a 5x5cm grid and charge on those dimensions even if your design is much smaller. I often look at other people’s OSH-Park designs at flickr site to see how far they stretch the 2 layer and 4 layer capabilities.
[ 01.10.2015 ] Bare boards arrive in the mail. They usually have rough snap-off edges which are easily filed down with a metal file.
[ 01.12.2015 ] Surface Mount Assembly begins. My tools are a 10x/30x microscope, a Weller-Ungar 921ZX soldering station with a screwdriver tip, GC Electronics Liquid solder-flux 10-4202, Kester “44 Rosin Core” lead solder 66/44 0.5mm .020″, Chem-Wik 0.075″ solder wick, Isopropyl Alcohol 99.8% IPA, Cotton Swabs, Dental Pick, Tweezer and “Dexter” leather gloves. I also have a 4″ surplus case fan at the back of my microscope to take away the fumes.
I always start by placing the QFP 1st as alignment is crucial with 0.5mm pitch between pins. Once the package is perfectly aligned ( 10x magnification ) I pour solder flux liberally along the perimeter. Flux is amazing stuff, not only does it perform Jedi mind control on molten lead to seek out copper and avoid solder mask – but it is wonderfully sticky stuff and does a fairly decent job of keeping the QFP from drifting out of alignment. That said – I always tack down the corners first with just a bit of solder and then pour the solder on thick – rolling across all the leads. End result – complete ugly mess, shorts everywhere – but the leads are all attached to their pads in perfect alignment.
Pass-2 ( you knew there had to be a pass-2, right ? ) – Solder Cleanup. The wick combined with the flux on the board magically sucks up the excess solder shorting all the leads. This step gets really hot really fast. I protect myself ( finger tips ) with my Dexter gloves ( thin unlined leather ) so I can position the wick and not burn myself. I protect the chip by only wicking about 4 pins at a time then pull back and let the IC cool down for a few seconds before proceeding. Takes patience but perfectly soldering an internally fried chip to a board is a real bummer. I do own a nice hot air reflow station where I can remove bad ICs -but I generally would rather just start a new board assembly from scratch than rework a bad one.
Pass-3 : This pass is optional, but is worth the effort. Apply lots of IPA ( the kind that makes you go blind – not the tasty beer ) and cotton swab scrubbing to remove all the flux.
Pass-4 : With the QFP clean, I crank my microscope up from 10x to 30x and go around to each pin with a dental pick and check for bad solder joints ( loose pins ) or any shorts. I usually don’t find any, but the time to check is before all the other components are soldered to the board as access to the QFP pins becomes difficult if there are other components around.
Once the QFP is on everything else is pretty straight forward. I only use 0603 for Bypass caps ( 0.1uF ) and 0805 10uF Bulk Caps and 0805 resistors. This speeds up assembly as I don’t need to look up each component in the design file, I can tell just by the pad size and what its connected to determine what to place. For example – I never connect a 0805 resistor between power and ground – so it must be a 10uF bulk cap. For the small SMT 0603s and 0805s I drop a bit of solder on 1 of 2 pads, then apply to component with tweezer and resolder the 1st pad to the component, then with the component firmly ( fully planar ) attached to the board, I apply solder and the iron tip to the 2nd pad. After this, the 1st pad usually needs some more solder to make a good looking connection. Thats it – I’m done with assembly!
Before test – I take a moment to reflect and decide what I would do differently to make assembly easier in the future. For this design the microUSB connector was a problem. It is designed for solder paste and oven reflow assembly as the leads are recessed behind the shield housing. I was able to solder them eventually, but a little more space between the connector and QFP would have been better. Mini-USB is MUCH easier to hand solder. Another issue I discovered is the shield extending behind the leads unexpectedly results in the shield resting above my 5V trace on the top side. The solder mask is the only insulation preventing a short from 5V to shield return. Prior to plugging into my computer, I applied my 5V DC supply to 5V PCB rail and the shield and confirmed no short. This is OK for a one-off, but I immediately created a new “fixed” version of this design and moved the 5V trace south about 0.010″ to clear the shield. For $3.50 I will probably fab out this “fixed” version and scrap the remaining 2 unstuffed PCBs of Gen-1 if I decide I need more than 1 unit. The micro USB connector was the only issue, so moving on….
Time for test. Plug and pray a micro USB cable from my computer into the board. And look at that! COM5 ready for use.
1st test is to send 9,600 baud to my scope. Bit length is about 100us, or roughly 10,000 Baud.
2nd test to send 921,600 baud to my scope. Now the bit length is about 1us, or roughly 1Mbaud.
3rd and final test, run my Powershell script that talks directly to FTDI device driver DLL and configure port for 12Mbaud.
Excellent! I’m in business. I now have a USB 2.0 to 12Mbps UART serial interface into my FPGA designs that is electrically and mechanically compatible with my existing FPGA boards ( that are designed for the industry standard FTDI cable ). That ends my Black Mesa activity for tonight. Next tasks are to change my FPGA design for the faster baud rate ( simple divisor setting in Verilog ) and establish Backdoor communications (Register Reads and Writes using BD_SHELL.exe ) and then time SUMP.exe data dumps from FPGA to computer and compare date rates between 1Mbps cable and 12Mbps board. Due to Windows and Powershell limitations – it may or may not be faster. If it is faster ( like 10x faster ) – my next iteration of the design is ready to be assembled. This uses the same chip, but interfaces using 16 wires over a Nano x16 header instead of the FTDI 2 wire 1×6 connector. Spec says transfer rates should be 40 MBytes/Sec ( 320 Mbps ) – which theoretically would be 27x faster than my existing design that is already 12x faster than my existing FTDI cable. That project is for another day however.
[01.11.2015] Succeeded in converting my RaspberryPi to mount an ext4 /root filesystem on a USB Flash Drive instead of the microSD card ( normal Pi boot location ). Process was actually quite simple. I will outline the entire process from Blank uSD and USB to working.
RASPBIAN Debian Wheezy Version:December 2014 Release date:2014-12-24
Step-1) Download latest Raspian *.IMG file from http://www.raspberrypi.org/downloads/
Step-2) Use Win32DiskImager on Windows PC to write IMG file to uSD card.
Step-3) Boot the Pi ( it needs to expand the new filesystem on the uSD ). Go through the normal raspi-config process for timezone, etc.
Step-4) Reverse Step-2 on Windows7 and create new IMG file from reading the uSD. This is now a personalized version of Raspian you can use for USB or uSD.
Step-5) Write the new IMG file to USB stick. This will copy both the boot ( FAT ) and the root ( EXT4 ) partitions to USB. Pi will only use the EXT4 partition from USB.
Step-6) On Windows, edit uSD card file cmdline.txt from the boot ( FAT ) partition.
From: root=/dev/mmcblk0p2 ( the uSD )
To: root=/dev/sda2 ( the USB )
That is it. When the Pi boots, it will ignore the old ext4 root filesystem on /dev/mmcblk0p2 and use /dev/sda2 instead. I had 2 goals in doing this process, goal-1 was to put the filesystem on a more robust media than uSD. I have had bad experience with corrupted filesystems on SDs on Pi’s in the past from improper power removal without shutdown. Goal-2 was faster boot times. Sadly, my boot times were unchanged at 30s to text login for both uSD and USB. I purchased the fastest USB flash media I could find ( SanDisk USB 3.0 16GB for $11 ) – thinking that even though the Pi is USB 2.0, the flash access ( latency, etc ) would be faster. I suspect the Linux boot process executed on the 700 MHz ARM is the actual bottleneck.
Good info here on Pi boot process
Although I am a hardware engineer, I have past experience doing software development, mostly for things like embedded hardware ( HC11, 68K, ARM in C and assembly ) but also some PC for test fixtures, etc. Pre-college ( and pre-internet ) days I taught myself computers via BASIC and Assembly programming on TRS Model-I ( 2 MHz Z80 1980 ) then the Apple ][ (1984 – 1 MHz 6502 ) before finally coming to my senses in 1990 and buying an IBM clone and discovering C when I entered the Electrical Engineering department at the UW and realized Apple was not where its at ( sorry Mac fans ). These days I mostly write a lot of Perl and Python scripts for chip development and testing. The chips themselves I design in Verilog and VHDL – which is definitely NOT Software Development ( its inferring Flip-Flops and Combinatorial logic – not inferring assembly instructions for a CPU – huge difference ). Anyways – I have created a couple of open source software projects that make me a more productive Electrical Engineer.
[ Chip Vault ] ChipVault I wrote in 2001 when I realized that ASIC and FPGA designs were rapidly getting too big to manage all the RTL design files manually and software oriented IDEs weren’t well suited for hardware designs. It was written in Perl and at 11K lines – ridiculously large for a Perl script. It runs on Linux ( and Solaris initially ) and does basic IDE hierarchy management and revision control for chip designs. Back in 2001 when EE Times was still an actual newspaper trade publication, I was phone interviewed by Richard Goering – the industry EDA expert for a nice article on ChipVault.
[ bd_shell ] bd_shell I wrote just recently in 2014. It was inspired by all the BASIC programs I wrote for my TRS-80 Model-I and Apple 2 in the 1980s. BASIC had commands Poke and Peek for easily writing and reading to hardware IO ports which were all open to user access. With 1 MHz CPUs I could build wire-wrap circuit boards with TTL 7400 series 5V parts from RadioShack and Jameco that would plug into my 1st two computers and actually decode bus IO cycles. By writing Poke and Peek commands in BASIC I could access my hardware directly and flash LEDs, beep buzzers, etc. As a kid in the 1980s it was perfect timing to learn hardware and software on your own. I studied the Apple 2 schematics in detail and definitely grew up in awe of Steve Wozniak – he definitely deserves more credit then he has received for starting the personal computer revolution. Just compare the Apple2 with the Altair that Bill Gates and Paul Allen wrote BASIC for. That said, Woz by himself was just a ( extremely talented ) hardware hacker – combined with Jobs they became a virtual Tony Stark ( or Elon Musk ) virtual entity. This open computer era inspired the RaspberryPi team to create their wonderful little open and low cost Linux computer. It challenged and inspired me to follow a career path into Electrical Engineering. The personal computer revolution and evolution was pretty exciting from 1980 to 1995 – then things just kind of stopped. Sigh.
Modern computers make it VERY difficult to communicate to hardware peripherals at a low level without writing root privilege device drivers. Inspired by the early open computer days I wrote bd_shell.exe as a UNIX shell like interface for communicating to hardware over a 2 wire ( “Backdoor” ) FTDI serial interface to USB. It inherits low level hardware access commands from BASIC ( Poke became “w” and Peek became “r” ) and also powerful UNIX shell features like piping, nested scripting, command history, variables, etc. bd_shell is written in Microsoft Powershell, a scripting language primarily intended for SysAdmins – but it binds to .NET components – making it as powerful as C# without the VisualStudio overhead. I stumbled across this awesome Powershell script by Ingo Karstein called PS2EXE that translates a *.ps1 script into a .NET *.exe windows executable. What this means is that I no longer have to write windows Form apps in C# and using VisualStudio ( license headache ). Now I can develop a Windows Form app in PowerShell as a script, test it and only ~compile~ it to a .NET executable when I’m ready to share with people. I don’t need VisualStudio at all even. Just some decent C# reference books. Although the syntax of Powershell is a bid odd, the ability to rapidly develop a software application as a script and then compile into an executable for deployment is very much the best of both worlds. I’m hooked.
[ sump ] SUMP.exe is my own version of a SUMP logic analyzer. The original SUMP project was designed in 2007 as an external logic analyzer using a low cost Xilinx FPGA eval board for capturing external electrical signals to all available RAM inside the FPGA.
The original developer published the serial communication protocol and also wrote a Java based waveform capture tool. The simplicity of the protocol and the quality and maintenance of the Open-Source Java client has inspired many new SUMP compliant projects such as:
‘Open Logic Sniffer’ : https://www.sparkfun.com/products/9857
I created SUMP RLE hardware following original SUMP protocol http://www.sump.org/projects/analyzer/protocol/ and it maintains compatibility with the open source Java Client ‘Logic Sniffer’ by Michael Poppitz 2006 and actively maintained by J.W. Janssen at: http://www.lxtreme.nl/ols/ . After I finished the hardware ( a variation of SUMP that stores samples with Run Length Encoding compression to conserve FPGA RAM ) I l took my recent PowerShell experience and created the SUMP.exe GUI to add new features to my own version of SUMP. It provides a user configurable trigger menu that configures the hardware and then reads the acquired data and displays in a waveform window with basic cursor measurements.