[ 01.14.2015 ] Fully evaluated my new USB 2.0 FT232H board tonight. Modified my Xilinx Spartan6 Nano FPGA design to PLL the 40 MHz reference XO to 120 MHz instead of 80 MHz so I could get a perfect UART divisor to 24 MHz for 12Mbaud communication. Then I modified my SUMP.exe application to configure the FTDI DLL for communications at 6 Mbaud and 12 Mbaud instead of normal 921,600 baud. Learning how to communicate to the FTDI DLL from Powershell ( I had to reverse engineer C# example code ) in December 2014 was what started this project to begin with as it allows configuring baud rates faster than Windows COM limits (921,600). With everything modified I had SUMP measure the event dumps of 8KB FPGA RAMs using the different physical interfaces ( USB 1.0 FT232R vs USB 2.0 FT232H ) and different software interfaces ( Windows COM driver versus FTDI DLL ). My new board is definitely faster ( 3.5x ) but not the 12x faster that I had hoped for. Would it be faster with a C or C# application instead of Powershell? Probably, I’m not about to go down that path though.
USB 1.0 FT232RL COM4 @ 921,600 baud : SUMP Dump took 248ms or 262Kbps. 1.00
USB 1.0 FT232RL DLL @ 921,600 baud : SUMP Dump took 240ms or 273Kbps. x1.04
USB 2.0 FT232H COM4 @ 921,600 baud : SUMP Dump took 257ms or 255Kbps. x0.97
USB 2.0 FT232H DLL @ 921,600 baud : SUMP Dump took 237ms or 277Kbps. x1.06
USB 2.0 FT232H DLL @ 6,000,00 baud : SUMP Dump took 83ms or 790Kbps. x3.02
USB 2.0 FT232H DLL @ 12,000,00 baud : SUMP Dump took 71ms or 923Kbps. x3.53
So, I suspect I may have hit a Windows / Powershell limit at around 900Kbps payload at 12Mbaud using the default asynchronous 2-wire interface. This probably puts a kabosh on my next board with the FT232H that has the 40MByte/sec 8bit FIFO interface ( 320Mbps theoretical ). I am skeptical I will get any faster than the 12Mbaud asynch serial and its a lot of Verilog writing and debugging to implement the FIFO interface inside the Spartan6 FPGA, not to mention consuming a full Nano x16 bus connector. I like to follow the Ethernet evolution model of not changing until you can achieve a 10x improvement. 3.5x improvement is good – but not 10x. I think I may have to make the trade off of rapid SW development in a scripting language ( Powershell ) versus fastest possible HW interface requiring low level compiled code ( C, C++ ), since SUMP transfers RLE compressed data anyways – really, I guess I’m not in THAT much of a hurry as it is transferring the entire event dataset in 250ms at 921,600 baud – which isn’t too bad really, that’s not even enough time to get a cup of coffee.
Question : FTDI just announced the new chip FT600Q that does USB 3.0 Superspeed ( 5 Gbps ) in a MLF56 package. Do I design a Nano x16 peripheral board for one when they ship end of this month? Maybe – it would be a great technical achievement to get 5Gbps SERDES chip – “Black Mesa Labs – Delivering 5Gbps SERDES on 2-layer PCBs”. Will it be faster than my new FT232H USB 2.0 ? probably not constrained by Powershell and Windows. Great challenge regardless. Wait and see I suppose…