Mesa Bus Protocol

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Enclosed text file ( mesa_bus  ) is the open-source  Mesa Bus Protocol for transferring bytes between CPUs and FPGAs. It is intended to transfer data between 50 Kbps up to 10 Gbps over UART to SERDES links with just a few wires and very little hardware overhead. It is a very small gate foot print byte transport protocol for encapsulating and transferring payloads of higher protocols (0-255 bytes per payload). Think of it like a cross between Ethernet and USB 3.1. The advantages Mesa Bus Protocol has over USB, Ethernet and PCI is that it fits easily within a $3 FPGA and may be bus mastered either by a PC with a FTDI cable or any old ARM/AVR Arduino CPU (or RPi) with just two standard UART serial port pins. As it is ASCII based, Mesa Bus Protocol is also very portable to wireless devices such as Bluetooth SPP and the RockBLOCK satellite modem for the Iridium network .

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Have you ever placed a regular envelope inside an interoffice envelope? Mesa Bus is that interoffice envelope. Where Ethernet transfers UDP, TCP, HTTP,etc packets without higher level knowledge – Mesa Bus can transfer SPI, I2C, Digital Video, 32bit LocalBus,etc  from chip to chip without protocol knowledge.  Mesa Bus works with up to 254 devices with only 2 wires between each device. Black Mesa Labs currently uses Mesa-Bus with the Mesa-Logic MCM FPGA and BD_SHELL.exe windows executable, Python, or an Arduino-Zero ( ARM ) as bus master. Payloads have been digital video ( 800×600 at reduced frame rates over a 40 MHz synchronous Mesa Bus link ) and 32bit local bus write and read cycles (PCI-ish) to FPGA registers and also for FPGA flash firmware updates. Mesa Bus Protocol fully supports prototyping embedded software 1st on a PC in a rapid scripting language like Python as it is clear ASCII that may be transported over a standard FTDI cable or Bluetooth SPP connection.

 

 

 

 

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Mesa Bus Protocol

6 thoughts on “Mesa Bus Protocol

  1. Geoff Sokoll says:

    Kevin, what are your thoughts about implementing this on a microprocessor instead of FPGA (at least for lower speed operation using SPI) ?

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    1. Do you mean as a slave device? So long as the uP can be configured as a slave, it should work just find. I’m already using a RaspberryPi as a SPI MesaBus master. For the SUMP2 LogicAnalyzer for IcoBoard Lattice FPGA board I had no choice as that board routed the Pi’s UART RXD and TXD to a configuration CPLD instead of the FPGA. Check out SUMP2 for IcoBoard if you would like to see Verilog and Python for MesaBus slave and master.

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      1. Geoff Sokoll says:

        I’m actually thinking about as both master and slave devices. I’m currently doing some concept development work on a data acquisition system involving a master module and multiple slave modules.

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