2017.02.07 : BML has been very much enchanted with the Lattice FPGA boards for Raspberry Pi, IcoBoard , BlackIce and IceHat. The IceZero board is a BML creation that attempts to combine the best features of all 3 boards into a single design. Hackaday article here.
[ IceZero Block Diagram ]
[ IceZero features common with other designs ]
- Fully Open-Source Hardware and Software Design.
- Lattice ICE40HX4K FPGA that supports Clifford Wolf’s Project IceStorm tool chain.
- Interfaces to Raspberry Pi 2×20 GPIO Header for both power and bus interfaces.
- PROM programmable directly from Rasp Pi, no JTAG programmer required.
- External SRAM, supporting soft CPU core designs ( code execution ).
- Extra large SPI PROM, supporting soft CPU core designs ( code storage ).
- Industry standard PMOD expansion headers
[ IceZero features that are BML specific ]
- Mesa Bus Protocol 32 MHz SPI link between CPU and FPGA.
- 2-Layer PCB design. Orderable via OSH-Park or Gerbers for Downloading.
- FTDI 1×6 USB Serial Cable header for use with PC instead of Pi ( or as a soft CPU debug Trace Port ).
- Single Pi UART plumbed to FPGA for muxing to multiple external serial devices.
[ Board Design ]:
Please see the IceZero Hardware Design Document and check back for updates.
IceZero is drawn as a 2-layer PCB using CopperConnection from RobotRoom, an excellent PCB drawing tool. Board dimension are 2.57×1.18 inches (65.20×30.02mm) , or the near equivalent outline of a Raspberry Pi Zero.
Top:
Top side contains FPGA, SPI PROM, 3 LDOs ( 3.3V, 3.3V, 1.2V ) a OK LED, misc passives and optional 0.100″ PMOD connectors ( 2×6 and 1×6 ) and a single 1×6 0.100″ FTDI header.
Bottom:
Bottom side contains 100 MHz MEMs oscillator, 256Kx16 SRAM and misc passives.
[ Bill of Materials ]
Qty-1 : 220-1572-ND : ICE40HX4K-TQ144 : IC FPGA 107 I/O 144TQFP : $5.77
Qty-1 : 706-1306-1-ND : IS61LV25616AL-10TL-TR : IC SRAM 4MBIT 10NS 44TSOP : $3.36
Qty-1 : 1473-1484-1-ND : SIT8008BI-12-XXE-100.000000G : OSC MEMS 100.0000MHZ LVCMOS SMD : $1.23
Qty-1 : 557-1562-ND : N25Q128A13ESE40E : IC FLASH 128MBIT 108MHZ 8SO : $1.82
Qty-2 : BU33TD3WGCT-ND : BU33TD3WG-TR : IC REG LDO 3.3V 0.2A 5SSOP : $0.28
Qty-1 : BU12TD3WGCT-ND : BU12TD3WG-TR : IC REG LDO 1.2V 0.2A 5SSOP : $0.28
Qty-10 : 1276-5086-1-ND : RC1608J103CS : RES SMD 10K OHM 5% 1/10W 0603 : $0.01
Qty-1 : 1276-5062-1-ND : RC1608J102CS : RES SMD 1K OHM 5% 1/10W 0603 : $0.01
Qty-4 : 1276-2087-1-ND : CL10B475KQ8NQNC : CAP CER 4.7UF 6.3V X7R 0603 : $0.03
Qty-16 : 490-9730-1-ND : GRM188R70J104KA01D : CAP CER 0.1UF 6.3V X7R 0603 : $0.03
Qty-1 : 641-1332-1-ND : CDBU0520 : DIODE SCHOTTKY 20V 500MA 0603 : $0.22
Qty-1 : 160-1176-1-ND : LTST-C170CKT : LED RED CLEAR 0805 SMD : $0.15
Optional:
Qty-1 : 2×20 0.100″ Straight Female Connector ( PI GPIO )
Qty-2 : 2×6 0.100″ Straight or Right Angle Female Connector (PMOD)
Qty-2 : 1×6 0.100″ Straight or Right Angle Female Connector (PMOD)
Qty-1 : 1×6 0.100″ Straight or Right Angle Male Connector (FTDI)
WARNING : The Micron 128Mb SPI PROM is end-of-lifing from DigiKey, so future builds will use a different PROM. Considering switching to Micron 64Mb N25Q064A13ESE40F or Cypress 64Mb S25FL164K0XMFI010 for cost and availability reasons. FPGA itself only requires 1Mb, everything above that is useful for soft CPU development for code storage. 64Mb at $0.85 is nice compromise.
[ Ordering IceZero ]
Right now, ordering bare PCB fabs is the only method for getting an IceZero board. Click on this link for ordering Qty-3 PCBs for $15 from OSH-Park. If there is interest, I will send Gerbers out for fab in China and could PayPal sell and ship single bare PCBs within the U.S. for maybe $5 – TBD. You may also optionally download the OSH Gerbers or CopperConnection layout files. All files are provided complete AS-IS and are provided under the CERN Open Hardware Licence.
[ IceZero License Statement ]
This project is licensed with the CERN Open Hardware Licence v1.2. You may redistribute and modify this project under the terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
This project is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.2 for applicable Conditions.
[ FPGA Programming ]
The Python script ice_zero_prog.py may be used for downloading a Lattice PROM file into the SPI PROM from a Raspberry Pi. This PROM utility is available on GitHub.
[ SUMP2 Sample Design ]
A SUMP2 Verilog sample design for the IceZero is available on my Dropbox. This uses the same Pi software as SUMP2 for IcoBoard. A very important feature of the IceZero sample design is that it may be used with zero FPGA experience as both a Logic Analyzer and a generic GPIO port expander, providing 24 software defined pins for things like reading switching, driving LEDs and even PWM outputs for servo control.
[EOF]
Black Mesa Labs 
[…] hats for the Raspberry Pi. Instead going out and buying one of these boards like a filthy commoner, he decided to spin up his own FPGA Pi accessory. This IceZero FPGA board combines the best features from other FPiGA boards, and does it in a form […]
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[…] hats for the Raspberry Pi. Instead going out and buying one of these boards like a filthy commoner, he decided to spin up his own FPGA Pi accessory. This IceZero FPGA board combines the best features from other FPiGA boards, and does it in a form […]
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Hi,
Thanks a lot for this project, I have purchased 3 pcb and I can’t wait to test them.
I have just a question, I live in France and the costs of shipping of Digikey are expensive, so I think of placing order to Mouser and there is not N25Q128A13ESE40E in stock.
Do you think I could replace this reference by the S25FL127SABMFV101 ?
Thanks by advance for your reply.
Best regards.
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That part looks fine. I need to pick a new PROM for the BOM. I chose the Micron 128Mbit just to grab the largest density that Lattice JTAG programmer supported. Now that I am writing PROM myself from ice_zero_prog.py, I can use whatever device I like so long as the readback is standard protocol ( should be ). I am considering this 64Mbit Cypress device as it is only $0.85 S25FL164K0XMFI010. The FPGA itself only required 1Mbit, the extra space is for people wanting to do soft CPU core development for code storage.
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Thanks for your reply.
I am going to try the S25FL127SABMFV101.
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Just assembling – I assume 4.7u caps go on “10u” pads?
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yes, 4.7u. 10u would work fine too.
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where is the schematic. I bought all the parts and the boards from OSH. Need to know how to mount smaller parts and where.
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No schematic available. Regarding placement, please look at the silkscreen layers. “10u” may be either 10u or 4.7u caps.
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If I disconnect a IceZero from the host Pi, are there any limitations on the pins in the 2×20 header? Besides voltage and ground, do they just run directly into the ICE40HX4K? I assume the 17 GPIO are free, but wonder about 11 more pins from SPI and I2C and serial.
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With the exception of the PROM pins, the 2×20 pins that are routed to the FPGA would be available as general purpose LVCMOS 3.3V IO.
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I just completed mine but I am using a Pi Zero W. Here is a picture.
https://drive.google.com/file/d/0B3J8EE9TfcTSVVY1MFVzSlpOdDQ/view?usp=sharing.
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Nice Work! Good example of how the 2×20 header may be soldered topside and have the Pi-Zero on top, with IceZero on bottom ( this doesn’t work with regular Pies since the header is pre-installed ).
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Yeah we are building 3 of them since oshpark does pcbs in batches of 3. I might make the other 2 different. This build was for a colleague at work who had male pins on his Pi zero. I will make mine compatible with the Pi3 and get a Pi Zero to match.
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Any suggestions for replacement flash? Both the 64 Mbit Micron and Cypress look EOL’d.
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Cypress S25FL164K0XMFI010 is available at Mouser
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[…] Trenz electronic only shared part of the documentation, but you’ll find everything on a blog post on Black Mesa Labs with the design files licensed with the CERN Open Hardware License v1.2, and […]
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Hey anywhere we can get a prefab for this?
I would like to test.. but I’d really like to just get stuck in to programming without having to order parts and do the solder.
If the full fab kit isn’t available would anyone be willing to fabricate and sell a few to me?
I live in Melbourne, Australia.
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Yes! Trenz Electronics in Germany makes them fully assembled ( and tested ). https://shop.trenz-electronic.de/en/TE0876-01-IceZero-with-Lattice-ICE40HX?c=188
Shipping to the US was a bit pricey, about the price of a single board, so I would recommend buying 2-3 IceZeros at a time.
See latest blog post regarding sample GPIO+Servo design – it uses the Trenz version.
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I built an IceZero during winter, but the project has been dormant for a while,
Had some problems with the bitbanged SPI interface to the flash chip, which did not work for me, so i soldered wires from the RPI SPI interface and use spidev interface for programming the flash instead
Restarted it this week and tried the IceZero Raspberry “Servo Example” bitfile, and my icezero showed signs of working.
Tried a generated bitfile from own verilog code and yosys, which did not work when i downloaded it to the flash on the IceZero
The differences turned out to be a 79 byte header in the bit-file for the SPI-flash, adding 79 zero bytes to the beginning of the bitfile, and reflashing made the FPGA work!!
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I built mine but I put the header connector on wrong orientation (so pins 1 and 2 from the board were going to 39 40 on the Pi zero) and connected it briefly to the pi. I desoldered the connector (was a real pain and I had to snip off most of it because desoldering 40 pins is a pain). Now, I need to clean it up and put in a new connector. I hope I didn’t zap anything.
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Check to see if any of the 5V power pins from the Pi were connected to any of the FPGA or PROM pins. If they were, those devices were probably fried.
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Can the icezero board be programmed using a icoUSBaseboard?
I have both icoboard and icezero but did not yet try out the latter on the icoUSBaseboard.
Don’t want to venture in breaking the icezero board at first usel
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No,
The IceZero is programmed via bit-banging the PROM over Pi GPIO pins. The IcoBoard I believe has a CPLD on it that takes in serial streams.
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Why do I see a 8.33 MHz clock on the CK lines but no 100 MHz on the OSC? I have just power and gnd connected to the board and no PI at the moment?
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Are you assembling this board from the original BML Gerber design, or is this an assembled version from Trenz? The oscillator should definitely output 100 MHz if the correct device is installed. Maybe put an O-Scope on the 3V rail and make sure there aren’t supply problems. A missing bulk cap ( 4.7 uF ) could definitely result in your power rail oscillating at a strange frequency.
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Original design. My colleague soldered the board. Now, I can’t tell where the four 4.7uF and the 16 0.1uF are located? Its hard to tell from the board layout without a schematic. Perhaps he swapped one of the caps since they all are the same size. I will attempt to measure them with the power off.
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The 10uF ( or 4.7uF ) bulk caps are directly underneath the LDO section (SOT23-5s). All the 0.1uF caps should be by the ICs and Oscillators.
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I am getting all kinds of range of capacitances. Perhaps all the components are affecting my readings.
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I think the Oscillator is mounted correctly.
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Strange. If the rails look okay, next step would be to confirm the oscillator is working stand-alone – a bit of a pain – requiring hot-air to remove I’m afraid. One other possibility is that your PROM contents ( blank presumably ) is configuring the FPGA and the FPGA is driving out the CK net. Easy enough to check by holding off configuration. The RST and SS nets going to the RaspPi connector can be tied to GND I believe and that should hold off configuration.
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okay I am getting a 100 MHz (messed around with the solder pads and reheating and adding more solder to the OSC part) on the CK in center but the CK pin on the pi header is a square wave much slower than the 100 MHz (around .7.86 MHz). Is that right? Are they the same signal?
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Oh – that is correct. The “CK” pin on the Pi Header is for the FPGA configuration via the SPI PROM. This is generated by an oscillator internal to the FPGA and is completely unrelated to the external 100 MHz oscillator. When the Pi programs the PROM, it bit bangs a clock on this “CK” pin to the SPI PROM.
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I built a board from the gerber files here and was able to load a test bin that comes with icezprog, but I am a little lost on how to get sump2 working. Can I use the files from AppData.tgz from the icoboard page or do I have to build the project from the dropbox link here? I do not have iCEcube2 and am not sure how if possible to build the project with the IceStorm tools. Any assistance would be appreciated.
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The RaspPi software for the icoboard build is 100% the same as for the IceZero. The only difference you need to worry about is the top_bitmap.bin file for the FPGA itself. So use BOTH the links referenced here. “A SUMP2 Verilog sample design for the IceZero is available on my Dropbox. This uses the same Pi software as SUMP2 for IcoBoard. ” Grab the FPGA firmware from one ( and load the prom with it ) and grab the software from the IcoBoard project.
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Ok, I was able to load the firmware and start sump2.py. If I start SUMP2 without the SUMP2 firmware, it correctly reports that it cannot find the hardware and if I have the firmware loaded it proceeds in non demo mode. Running ico_gpio.py returns
00000001
00000002
ffffffff
5856b8bd
2016-12-18 11:26:37
READ 11223344
READ 00000100
READ 5856B8BD
so I am inclined to think that the FPGA is running and has a working SRAM, ROM and oscillator (my soldering job didn’t leave me with much confidence in that). Is that a safe assumption? Next I plan to learn the interface well enough to see if I actually have this working correctly. Thank you for the assistance.
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Congrats! Your FPGA is definitely alive. “11223344” is like an ID register, “00000100” looks like the Version and “5856B8BD” looks like the UNIX timestamp of when I ran synthesis on the build. Looks like you’re off to the races. Make sure and check with my Github website for updates to sump2.py. You should just copy these directly over to your Pi on top of the existing sump2.py. I’ve made a lot of performance and VCD changes recently.
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I am sorry. Looks like the board available on Trenz is also compatible with RaspPI. Can you please let me know how this board is difference from the one available on Trenz?
Will I be able to run your github examples using the board available with Trenz Electronic?
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Yes, my examples will absolutely work with the Trenz iteration of IceZero. The difference between the boards is the BML is a 2-layer PCB with 2 full 2×6 PMODs and 2 half 1×6 PMODs. The Trenz design uses a surface mount 2×20 Pi connector which bought some more space, plus is 6-layer PCB ( if I remember correctly ) and has 4 full 2×6 PMODs. It comes fully assembled and tested of course – which is a huge bonus. I bought 2 myself to ensure full compatibility with my example designs. https://shop.trenz-electronic.de/en/TE0876-02-Ice-Zero-with-Lattice-ICE-ICE40HX
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Would this support other boards that have the pi-2 bus interface? For example: https://www.pine64.org/?page_id=61454
As it’s more powerful than any of the R-Pi models circa 2018.
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I suppose if it has a compatible 40pin header that the Pi has. The IceZero uses the header for 5V power and also GPIO pins for SPI PROM programming. The SPI and UART pins of the RaspPi are also routed to the IceZero FPGA. All I/Os are LVCMOS 3.3V.
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Not sure if I’m missing something entirely or not but the BOM shows 16 cap’s @ 0.1uf and another 4 at 4.7uf. I am only seeing a total of 20 cap markers on the board files (including the 10u ones replaced with the 4 x 4.7uf as noted in a previous comment). Am I missing something or are these other two caps surplus? 14 x 0.1uf on the bottom side of the board. Thanks!
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I counted the same just now, 14 0.1uF and 4 4.7uF – the BOM is probably wrong.
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Will the following substitions work (I read as long as the cap voltage is higher it should be fine):
“RES SMD 10K OHM 5% 1/10W 0603” with https://www.digikey.com/product-detail/en/panasonic-electronic-components/ERJ-3GEYJ103V/P10KGCT-ND/134717
“CAP CER 0.1UF 6.3V X7R 0603” with https://www.digikey.com/product-detail/en/wurth-electronics-inc/885012206020/732-7939-1-ND/5454566
“IC FLASH 128MBIT 108MHZ 8SO” with https://www.digikey.com/product-detail/en/cypress-semiconductor-corp/S25FL127SABMFI101/1274-1045-ND/4142071
I ask as I built a board with the above replacement parts and I cannot get it to power up. I’ve run through checking voltage and continuity where possible and everything looks good but like I said, cannot get it to power up.
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Those component seem fine. When you say “cannot get it to power up” do you mean you provide 5.0V and then the 3.3V and ( 1.2V? ) rails don’t come up? They are simple LDOs. Are you current limiting possibly? Maybe a short somewhere?
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I provide 5V and I see both 3.3V LDOs output 3.3V as expected and the other putting out 1.2V. As stupid as this may sound, I’m expecting the LED to light up or show some form of activity and I am not seeing that. I’ve checked voltage into the pins on the FPGA and all are ~3.3V, same with LED I believe. I also cannot access it via the RPI I have it hooked up to (can’t see it from the OS), thus I figure something isn’t working as expected. I was checking for shorts on just about every place I could (visually for solder briding and with continuity using a multi meter). New enough in the hardware realm that I can figure my way around but trouble shooting is proving to be more difficult than expected 🙂 Thanks for the reply.
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I’m confused. Have you programmed a Firmware design into the SPI PROM? No LEDs will blink, etc unless there is a design loaded.
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I manged to get things going finally. I’ve actually integrated the ice40 into the kernel on a raspberry pi via work done the information at https://opentechlab.org.uk/videos:002:notes — That said, I am running into trouble programming the chip’s SPI PROM via the kernel. Could you confirm the correct GPIO for the CDONE 39 and the GPIO for RESET is 37? Thanks again for all your hard work on this!
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39 is GND. 37 = RST, 36=CLK, 33=MISO, 31=MOSI, 29=DONE, 32=CS_L. There are 2 programmers that exist already, my Python and Clifford Wolfs’ C version both for the RaspPi. See https://github.com/blackmesalabs/ice_zero_prog
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My friend soldered on of three boards (we ordered parts for 3 as that is the Oshpark min for pcbs. I never saw a clock on the oscillator chip and my collegians I wonder if it was a slider issue on the oscillator or FPGA. So it’s sitting in a box somewhere and I never completed it. Should I remove the FPGA or oscillator and try re-soldering them? How to debug? It might be a power issue.
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Figure out the clock oscillator. It runs indepedent of the FPGA and should be providing 100 MHz. Check to make sure you didn’t solder it down rotated 90o. Check the VCC pin for 3.3V and the OE for 3.3V ( from pullup resistor ). Put a scope on the output pin and look for 100 MHz square wave.
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I will try doing that. I did look for it on my work test equipment but don’t have much time to fiddle with it (we do FPGAs for larger science instruments at work). I don’t have a real scope at home but I did help fund the CrowdSupply project by a professor from NY. I need to get that working, mostly the software as it runs on all platforms before i can look at the 100 MHz wave. https://www.crowdsupply.com/andy-haas/haasoscope
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The professionally manufactured Trenz version is also available of course. Their shipping costs are high, so I’d recommend buying more than a single board at ~$35 to be cost effective. https://shop.trenz-electronic.de/en/TE0876-02-Ice-Zero-with-Lattice-ICE-ICE40HX
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I already dumped enough for parts (pcbs were cheap) and was going to give two away to my coworkers so don’t want put more $USD into it and at $34 Euros is way more than a Pi3 so not worth buying that one.
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First thank you for all the good work, I am really looking forward to see the OS toolchain in action 🙂
On the first steps, I got a little problem here and am hoping to not have bricked my iceZero board.
The IceZero (trenz version) could not finish the first programming (A contact issue – my fault) and I interrupted the process vie power off. Since then the only reaction I am getting out of icezprog is a “cdone is low” after a reset / erase first sector attempt or just nothing happening if I try to write the example binary. Am I getting something wrong here, did I brick my device and what could help here?
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As far as I know, it shouldn’t be possible to brick the iceZero. The RaspPi has full control of the FPGA during programming to give it complete access to the PROM. There is no bootloader or anything to brick.
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Hello Kevin and thank you for a lot the super fast answer (and the nice board design :-).
Good to know it’s not brickable, then I probably need to simply check the contacts again and switch the header (attempting to pressure fit it without soldering, so contact issues are expected). Should get to it this week…
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it actually was a contact issue…
I had to get a new header and tweak it for like 1h to get it running well.
Keep this in mind when trying to fit the header on a Pi Zero W without soldering…
Now everything works fine and I can playing 🙂
Thanks a lot again & keep up the good work!
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