IceZero FPGA Hat for RaspberryPi Servo Example

2017.07.04 :  Black Mesa Labs has some exciting news, the open-source IceZero FPGA Hat for RaspberryPi designed in December in 2016 ( and free to download Gerbers ) has been picked up by Trenz Electronics as a fully assembled product ready to ship and plug into a RaspberryPi. The Lattice FPGA is fully compatible with Clifford Wolf’s open-source icoTC tool chain for Verilog synthesis to FPGA bitstream.


This post provides an example design for expanding any RaspberryPi to have 32 GPIO pins and 6 PWM ( Pulse Width Modulators ) for driving Servos, LEDs, reading switches, etc. The best part is that NO FPGA design experience is required.  The simplest way to get up and running is to download the FPGA bitstream file, load it into the PROM using provided programming tool and then start your project with the example Python for configuring the 32 GPIO pins available on the IceZero ( 4 2×6 PMOD connectors ).

File_000 (6).jpeg


Step-1) Download either the Entire Big Design, or just the Bitstream and Python files.

Step-2) Plug the IceZero onto the RaspberryPi and use included python script to program bitstream into PROM.

%python gpio32_pwm6_te.bin

Note that the Bulk erasing procedure takes about a minute. Note, Clifford Wolf has written icezprog.c a C based PROM programmer for the IceZero that may be considerably faster. Worth checking out.


Step-3) If all is well, the 3 LEDs on the IceZero will be flashing again in a binary 3bit counter fashion.  Now you can look at the example example for configuring the 32 GPIO pins and the 6 PWM controllers.  The example design listens to 6 pushbuttons ( Increase, Stop, Decrease ) that are used for controlling 2 PWM blocks for 2 servos on a Pan/Tilt kit for a RaspberryPi camera.

Details regarding GPIO design – the reg_space.txt file is a detailed register description on controlling the 32 pins.  The IceZero has 4 PMOD connectors P1,P2,P3,P4 and there are corresponding registers for controlling them. For example:  The register PMOD_P1_CFG controls the pin configuration (CFG) for P1.  The 8 pins on P1 may be individually configured as input, output or PWM controlled.  PMOD_p1_CTRL then is used for reading status of P1 inputs and controlling P1 outputs.

Check back later for more details to be filled in.


IceZero FPGA Hat for RaspberryPi Servo Example