SUMP2.py as a VCD waveform viewer for Xilinx Vivado RTL Simulator

sump2_vivado_sim.PNG

2018.02.28 : The latest version of SUMP2.py ( available here ) GUI running under PyGame on any platform may now be used as a light weight rudimentary VCD waveform viewer for RTL simulations. This posting is a short tutorial on using the Xilinx Vivado Simulator ( available in WebPack ) as a command line simulation tool for Verilog and VHDL RTL designs. With the following setup, the command line Xilinx simulator will output a VCD file which may then be imported into SUMP2.py ( or GTKwave.exe ) for viewing.

The example design in this tutorial is a simple Verilog hierarchical design composed of top.v and counter.v.

[ top.v ]

module top
(
 input wire rst_l,
 input wire clk, 
 input wire load_en,
 input wire [7:0] load_d,
 output wire [7:0] test_out
);// module top

wire reset_loc;
assign reset_loc = ~rst_l;

//-----------------------------------------------------------------------------
// Example 8bit counter
//-----------------------------------------------------------------------------
counter u_counter
(
 .clk ( clk ),
 .reset ( reset_loc ),
 .load_en ( load_en ),
 .load_d ( load_d[7:0] ),
 .count_out ( test_out[7:0] )
);// module counter

endmodule // top.v

 

[ counter.v ]

module counter
(
 input wire reset,
 input wire clk, 
 input wire load_en,
 input wire [7:0] load_d,
 output reg [7:0] count_out
);// module counter
reg [7:0] test_cnt;

//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
always @ ( posedge clk ) begin : proc_cnt
 count_out <= test_cnt[7:0];
 test_cnt <= test_cnt[7:0] + 1;

if ( load_en == 1 ) begin
 test_cnt <= load_d[7:0];
 end 
 if ( reset == 1 ) begin
 test_cnt <= 8'd0;
 end
end

endmodule // counter.v

 

To import these files into the Xilinx Vivado Simulator, we will create a “project” file which lists all of the RTL files to be compiled. Both VHDL and Verilog are supported.

[ top.prj ]

verilog xil_defaultlib "./top.v"
verilog xil_defaultlib "./counter.v"

Two shell scripts ( either Linux or DOS for your platform ) are used for compiling and simulating the design files.

[ compile.sh / *.bat]

xvlog -prj top.prj
xelab -prj top.prj -s snapshot top -debug typical

[ simulate.sh / *.bat ]

xsim snapshot -tclbatch do.tcl

 

A collection of TCL files are used during simulation for both specifying which signals to capture to VCD file and also stimulus to force upon the design.  The addition to the Xilinx  simulator to accept “add_force” commands is significant as it means writing Verilog test bench files at the top level is no longer a requirement. This allows the Xilinx simulator to be rapidly used during module development and behaves as a low cost RTL simulator.

[ do.tcl ]

open_vcd
source wave.tcl
source force.tcl
close_vcd
quit

[ wave.tcl ]

log_vcd {/top/clk}
log_vcd {/top/rst_l}
log_vcd {/top/reset_loc}
log_vcd {/top/u_counter/*}
# Or recursively capture everything
#log_vcd [get_objects -r * ]

[ force.tcl ]

add_force /top/rst_l 0
add_force /top/load_d 00 -radix hex
add_force /top/load_en 0 
add_force /top/clk {0 0ns} {1 5ns} -repeat_every 10ns
run 10ns
add_force /top/rst_l 1
run 10ns
add_force /top/load_d 11 -radix hex
add_force /top/load_en 1; run 10 ns;
add_force /top/load_d 00 -radix hex
add_force /top/load_en 0; run 10 ns;
run 200ns

With these files all created, running the compile and simulate scripts should generate a dump.vcd file. The VCD file may then either be imported into SUMP2.py via this command:  %python sump2.py dump.vcd  or loaded into GTKwave.

Note: The latest version of SUMP2.py binds the F8 key as a macro to the “Reload_VCD” command. This is extremely handy as from a shell window, you can change your stimulus force file or Verilog, and re-run the compile+simulate scripts and then just press F8 with SUMP2.py in focus to reload the new VCD file. This removes the need to exit and relaunch SUMP.py every time a new VCD file is generated. GTKwave accomplishes the same with the Reload button ( two circular arrows ).

Note: SUMP2.py VCD import is really just intended for offline importing VCD files that SUMP2.py exported from a Logic Analyzer capture. As VCDs can vary from source to source, SUMP2.py is very likely to choke on all but the simplest VCD files.  For these more complicated use cases, GTKwave.exe is an EXCELLENT and robust VCD viewer.  This blog post is primarily aimed at SUMP2.py LA users who are familiar with the waveform viewer and would like to use it for viewing simple RTL simulations as well.

GTKwave is usually available here, but apparently SourceForge may be no longer? It is an awesome VCD viewer, so I would expect for it to pop up again ( maybe this is it on  GitHub? ).

gtkwave_vivado_sim.PNG

[ EOF ]

 

 

 

 

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SUMP2.py as a VCD waveform viewer for Xilinx Vivado RTL Simulator

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