SUMP2 – 96 MSPS Logic Analyzer for $22

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2016.22.22 : SUMP2 now also available for RaspPi+icoBoard here.

2016.12.13 : Great video on SUMP2 from Bil Herd at Hackaday.

2016.10.31: Thanx to SteveDC, a 3D printed case is now available for SUMP2 here.

2016.10.30 : SUMP2 5V Input shield is now available from OSH-Park for $5. BML can also design similar shields for RS232,RS422/485,LVDS and CAN Bus if there is any interest.

2016.10.24 : Black Mesa Labs has an ongoing mission to develop easy to use and fully capable open-source hardware and software tools that make engineering electronics easier. One such tool is this new low cost open-source logic analyzer called SUMP2 for people who otherwise work in the blind without an oscilloscope or logic analyzer on their bench top.  BML’s 1st incarnation called SUMP1-RLE in 2014 was a 16bit FPGA based logic analyzer that performed real-time hardware compression and decompression. The decompressed data was streamed out over USB using the open SUMP protocol ( hence the name ), allowing it to be used with the excellent Java software from the original 2007 sump.org project. The SUMP1-RLE project was later enhanced from just 16 triggerable events to also include 2 DWORDs of “data” ( additional 64bits of non-triggering non-compressed signals ) and advanced triggering options. Including the data DWORDs made SUMP1 a useful tool for complex FPGA development debugging of internal FPGA event nodes and data paths. These new features required new custom software, written by BML in .NET for Windows. The software was functional, but graphically slow and was mostly used for trigger setup and then exporting captured data as VCD files into GTKwave for viewing. SUMP1 also did not scale in width, depth or time, it was fixed at 16 events, 2 DWORDs and a 2^20 timestamp ( 1 Million Samples ) both in hardware and software. In 2016 BML decided to do a complete start-over on the SUMP RLE concept and developed SUMP2-RLE ( or just SUMP2 for short ). New Hardware, New Software. More features, better scaling – introducing SUMP2:

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The sump2.v verilog file is designed to work inside any FPGA or ASIC containing block RAM and scales in complexity from 1-4 bytes of events ( 8-32 triggerable and RLE compressible signals ) and 0-16 DWORDs of up to 512 non-compressed data bits. Depth and width of RAM scales on instantiation to best fit a wide range of FPGA technology. The full featured SUMP2 configuration is designed to be used on internal nodes within very large $100 – $1000 FPGAs. In this configuration for analyzing internal FPGA nodes it is very similar to proprietary FPGA vendor solutions such as Xilinx ChipScope and Altera SignalTap. SUMP2 has the advantage of being fully open and also offers RLE compression that can offer 10x – 1000x the time storage of similar FPGA logic analyzers not aided by hardware compression. Duty cycle hardware applications such a pulse-echo radar can readily achieve 5,000x compression using the new RLE engine with 2^32 timestamps. The scalability of SUMP2 also permits it to work in ultra low cost ( sub $5 ) FPGAs such as the Lattice iCE family. The Lattice iCEstick eval board at only $22 with included FTDI USB interface and PROM programming provides for a perfect SUMP2 platform for electronic debugging of Arduino and Raspberry Pi like projects involving 3V serial ports and GPIO. Communication between hardware and software over USB is all done using the Mesa Bus Protocol , an open serial protocol for transferring 32bit PCI reads and writes over UART, SPI and SERDES serial links between computers and FPGAs.

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To fit within the iCE40HX1K FPGA, sump2.v verilog RTL design is instantiated for 16 input events, no DWORDs and 1k depth of RLE capture RAM sampling at 96 MHz. The graphical backend software is sump2.py, a PyGame application used for arming the hardware and dumping and displaying the capture for analysis. Compared to the SUMP1 .NET app, the PyGame SUMP2 version is very fast. Although sump2.py supports exporting and importing VCD files, it is entirely not necessary to use a standalone VCD viewer such as GTKwave or Modelsim.

A simple example of a Unit Under Test.  Below pictured is a 10 MHz ( 100ns period ) oscillator driving a 74ACT161 4bit counter with a 74HC08 AND gate on the d(2) and d(3) upper bits of the counter. A push button switch to ground with a 10K pullup resets the counter. 8 nodes of interest are connected via Dupont ribbon cable to the iCEstick PMOD header.

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Short demonstration video of the sump2.py PyGame application:

The initial full capture of the reset button being released. The capture represents 4168 samples at 96 MHz using only 1K of RAM by utilizing RLE compression. RAM is hard partitioned 50/50 pre and post trigger.sump2_0003.png

SUMP2 has the ability of masking input events prior to arming which allows for greater RLE time compression. By double-clicking and “Hiding” the clk_10m signal prior to a new acquisition, the highly active clock signal is masked. This next capture without the 10 MHz clock is twice the length, or 83uS.  Also notice the very short reset switch bounce captured. Masking the LSB counter bits would further increase total capture time.

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Mouse scroll wheel can be used for zooming in and out in time, allowing for rapid detailed analysis and cursor measurements.

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Right-Clicking the mouse launches popup menus for tool selection.

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The left side popup allows for selecting a signal and then assigning it as a rising or falling edge trigger.

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Steps for building your own open-source SUMP2 Logic Analyzer for the Lattice iCEstick.

What is needed:

  1. $22 iCEstick from Mouser, Digikey or direct from Lattice. ( ICE40HX1K-STICK-EVN )
  2. Free FPGA Diamond Programmer software from Lattice.
  3. Windows Device Driver for the FT2232H USB chip from FTDI ( this may also be included with Lattice Programmer ).

and this free stuff from Black Mesa Labs:

  1. Bitfile for SUMP2 for the Lattice iCE40HX1K FPGA.
  2. bd_server.py – a Python TCP server for communicating to hardware over USB.
  3. sump2.py – a Python PyGame application. Handles triggers and waveform viewing.
  4. FPGA Design Files ( Optional, only needed if not using prebuilt Bitfile ).
  5. 5V Input shield PCB design in CopperConnection ( Optional ).

And finally, a bunch of text file documentation from Black Mesa Labs:

  1. Installation Instructions
  2. FAQ
  3. Program Launching instructions
  4. Troubleshooting guide
  5. Pinout for connecting flying leads to iCEstick
  6. Change Log for Software and Hardware
  7. Bug Report

EE Times Article by Clive “Max” Maxfield on SUMP2

Hackaday Article by Jenny List

Please enjoy SUMP2, a 96 MSPS 16bit 3V logic analyzer for only $22. Follow BML on Twitter for updates on SUMP2 and other open-source software and hardware projects from Black Mesa Labs.

EOF

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SUMP2 – 96 MSPS Logic Analyzer for $22

1″ 100W Hot-Plate for SMT Reflow

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[03.13.2016]

Black Mesa Labs has been using a $20 hot plate for a year now for soldering QFN ICs to PCBs using the BML Inverted Solder Ball reflow technique. This works great for soldering 0.5mm pitch QFN and LGA type packages that would otherwise require messy stencils and paste. Only issue so far has been the size ( 10″x10″x3″ ) and thermal mass of the commercial hot plate as it consumes precious microscope work area and unfortunately stays quite hot for 30+ minutes after a quick 4 minute single IC reflow job.  BML boards are mostly 1″x1″, so a 800W hot plate with a 6″ diameter heating surface is overkill for most jobs.

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Wanting something much smaller for a typical BML PCB – stumbled across this 24V DC heating element on Amazon for only $14. It is rated for 24V at 5-7 ohms ( or 4.8Amps ).  A surplus 19.5V DC 5A laptop power brick laying around BML seemed like a perfect match for this element.  BML has safety rules avoiding designs above 48V – so the 100Watt 20V DC supply coupled with the 24V element seemed like a great way to make a lot of heat in a small surface area in a short amount of time.

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First experiment was to see if this little element would reach +200C in under 4 minutes. Not wanting to cut up the laptop supply’s power connector – located this

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power connector adapter for only $5 and cut off the yellow Lenovo end of it and converted it to 0.100″ spaced Dupont connector instead. Hooked up a simple push button switch in line with the circuit – pressed the button and measured surface temperature with a digital thermometer – reached 200C in only 90 seconds!  Too fast for reflowing 40nm FPGAs unfortunately. Wanting to keep the 20V supply – needed to switch to pulse width modulation to slow down the thermal ramp to closely match solder reflow profile of 4 minutes to +200C. A relay? Nah – lets design a custom PCB with power FETs!

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After consulting with BML’s “all things analog expert on retainer” DP on how best to switch 100W at 20V – designed a small $2 2-layer PCB as a low-side switch using two IRLML6344TRPBFCT-ND 30V Power MOSFETs in parallel.  Design was drawn ( no schematic ) straight in CopperConnection Gerber drawing tool in less than 15 minutes and fabbed by OSH-Park in about 2 weeks for $2 for a ~1″ x 0.5″ 2-layer 0.8mm PCB.

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Rds On for this N-FET is 0.029 ohms at 5A ( or  725 mW ) which is near the 1.3W limit for the itty bitty SOT23 device. Not having any heatsinks other than the connection to the PCBs giant “Drain Plane” – opted to share the 5A load across two FETs in parallel. The N-Channel MOSFET’s Source is technically ground – but all the heat is dissipated through the Drain, so large pours on both PCB top and bottom were made to better dissipate the Rds On heat. Design is feed thru for + and – from the supply to the + and – for the load even though the + supply doesn’t touch the circuit at all.  Placed 3 different sized vias 0.125″, 0.079″ and 0.040″ so the board may be easily reused for other projects of various gauge wire needing high voltage and current switching.  A 100K resistor to GND ensures the FETs don’t turn on by themselves without a driver present (powerup Hi-Z) and a 1K series resistor to the Gate of both FETs limits the in-rush current. These Infineon  N-Channel FETs are only $0.29, come in a small SOT-23 package, can switch 5Amps from a 3V LVCMOS signal and are now BML’s go to device for power switching.

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Above is a Owon Scope capture of the FET turn on time ( Gate versus Drain ). CH2 ( Yellow ) is the Gate of the N-FET which is driven by LVCMOS 3.3V totem-pole from an AVR through a 1K series resistor. It takes 500ns for the Gate to go from 0V to 1V and then the FET turns on.  CH1 (Red ) is the Drain transitioning from pulled up ( via 1K thru the LED ) to clamping to GND. This transition takes about 2uS total.

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An Arduino Pro (above) was chosen as the PWM controller.  Most BML CPU designs are either RaspPi or Arduino-Zero based ( ARM 32bit ), but BML had this old Sparkfun board in a box and it was the right dimensions as a mechanical base for the project. The 1.5″ diameter heating element is suspended about 1″ in the air, so the wide 2″x2″ Pro board keeps everything from tipping over.
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Above picture shows everything cobbled together. A small piece of aluminum foil is wrapped around the element to keep flux from making a mess of it while under reflow. The heating element comes with 22 AWG solid wire crimped to it and extending about 2″ away. The wires are soldered to a 1×2 SIP connector which then mates to another 1×2 SIP connector on the FET board ( being able to remove the heating element from the circuit while under development was VERY important ).  The FET board is placed in the center of the Arduino Pro board atop some poster putty and held in place with the Enable wire (White ), the 1,500 resistor voltage drop network and a ground wire. The Pro can be powered from an FTDI USB cable of course, but to power it from the single Laptop supply, the voltage required dropping down from 20V to around 12V for the on board LDO.  Three 500 ohm leaded resistors each provide about a 2V drop while the AVR CPU is sipping 4mA, for a total drop of around 6V. A large 1K resistor provides 20mA to the red LED whenever the FET gates are turned on and the heating element is getting power.  Total cost was under $20 for the project – not counting the Arduino Pro in the junk box.MLX90614(E,K)SF-xxA.JPG

The Arduino was chosen over an FPGA as the PWM rate is really slow ( seconds ) and the Arduino makes it easy to expand the design and eventually interface to a Infrared Thermometer over I2C via existing tutorials and libraries.  Eventually the design could be expanded to measure the temperature at the surface of the FR4 under reflow for either reporting and / or control.  For now – the dead reckoning PWM method is plenty sufficient.  As the heating element contains very little thermal mass – it cools down in just seconds.

Above is the target solder reflow profile and below is the achieved profile as measured with a thermocouple on a scrap 1″x1″ FR4 PCB.

The GPL’d open source C++ source is available here hot_plate and is fairly straight forward.  When the button is pressed, the AVR starts a 4 minute PWM state machine that gradually increases the PWM duty cycle from 30% to 40% to 60% and then off.  Measuring a scrap piece of FR4 with a thermocouple mounted to it, an ideal reflow profile of 20-150C for 90 seconds, 150-200C for 90 seconds and finally 200-250C for 50 seconds was achieved. Pressing the button mid thermal cycle cancels the cycle. The AVR and giant Pro board is definitely overkill – but the PCB size made it a great platform to mount everything else to.

A word on safety – although this project is under 48V – the amount of heat it can generate could definitely start a fire if powered up in the wrong place ( under a stack of old newspapers for example ) .  To prevent any potential small fires from starting 3 levels of safety were built it. 1) the Arduino runs the heat profile only when the pushbutton is pressed and then automatically turns itself off after the profile time is complete. 2) The 20V 5A power to the electronics goes through a toggle switch. 3) The original laptop barrel connector is quickly and visibly disconnected from the setup when reflow is complete allowing the hotplate to be visibly disconnected from the power supply when not used.

Below is a YouTube video of a Lattice ICE5LP4K-SGN48 FPGA reflowing on the “Mesa Logic DIP” PCB using the BML Inverted Solder Ball reflow technique. This is a general purpose FPGA board on a 0.100″ grid providing 24 user IOs in a 0.600″ x 1.6″ package. This board has a destiny to reach 100,000 feet (~30km) this coming May as a HAB controller for a weather balloon. It will communicate with both an “on balloon” Raspberry Pi and with a ground station via a RockBLOCK Iridium satellite modem using Mesa Bus Protocol. Stay tuned to Black Mesa Labs for an upcoming blog on all the details of the custom HAB electronics.

 

 

1″ 100W Hot-Plate for SMT Reflow

Mesa Bus Protocol

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Enclosed text file ( mesa_bus  ) is the open-source  Mesa Bus Protocol for transferring bytes between CPUs and FPGAs. It is intended to transfer data between 50 Kbps up to 10 Gbps over UART to SERDES links with just a few wires and very little hardware overhead. It is a very small gate foot print byte transport protocol for encapsulating and transferring payloads of higher protocols (0-255 bytes per payload). Think of it like a cross between Ethernet and USB 3.1. The advantages Mesa Bus Protocol has over USB, Ethernet and PCI is that it fits easily within a $3 FPGA and may be bus mastered either by a PC with a FTDI cable or any old ARM/AVR Arduino CPU (or RPi) with just two standard UART serial port pins. As it is ASCII based, Mesa Bus Protocol is also very portable to wireless devices such as Bluetooth SPP and the RockBLOCK satellite modem for the Iridium network .

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Have you ever placed a regular envelope inside an interoffice envelope? Mesa Bus is that interoffice envelope. Where Ethernet transfers UDP, TCP, HTTP,etc packets without higher level knowledge – Mesa Bus can transfer SPI, I2C, Digital Video, 32bit LocalBus,etc  from chip to chip without protocol knowledge.  Mesa Bus works with up to 254 devices with only 2 wires between each device. Black Mesa Labs currently uses Mesa-Bus with the Mesa-Logic MCM FPGA and BD_SHELL.exe windows executable, Python, or an Arduino-Zero ( ARM ) as bus master. Payloads have been digital video ( 800×600 at reduced frame rates over a 40 MHz synchronous Mesa Bus link ) and 32bit local bus write and read cycles (PCI-ish) to FPGA registers and also for FPGA flash firmware updates. Mesa Bus Protocol fully supports prototyping embedded software 1st on a PC in a rapid scripting language like Python as it is clear ASCII that may be transported over a standard FTDI cable or Bluetooth SPP connection.

 

 

 

 

Mesa Bus Protocol

Mesa-Video : 800×600 Digital video for Arduinos over 2-wire serial Mesa-Bus

Mesa-Video : 800×600 Digital video for Arduinos over 2-wire serial Mesa-Bus

[ 08.30.2015 ]

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This post describes Mesa-Video, a low cost, low power, small size and fully Open Source Hardware and Software solution for providing 800×600 digital video for Arduino ( and other ) microcontrollers.  Mesa-Video makes it quick and easy to display text and 24bit color graphics from any MCU using a single UART serial port pin. Applications for Mesa-Video are embedded projects requiring video output and embedded developers wanting real time visibility into their system operation. Mesa-Video is the 1st of multiple Mesa-Modules planned. For a quick summary of Mesa-Video and Mesa-Bus, please read the very nice article at Hackaday by Richard Baguley from 09_01_2015.

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[ GPU SPI Bus Interface ] On the original EVEy Video board  ( shown above ) the native SPI interface for the FT813 GPU‘s is brought out to a “Nano Bus” header which was then bit banged with Python software on a PC going through a BML Nano3 FPGA (shown below) containing simple GPIO logic. This was perfect for initial board test and GPU bring up, but slow and needing a faster interface to PCs and micro controllers for a final product.

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[ The Arduino SPI Problem ] : A major problem with SPI ( and I2C ) on Arduino is that with shield stacking it is difficult to get more than a single shield device on the bus. SPI devices all require a unique chip select and I2C devices all require a unique address. This is all a bit like the pre-PnP era of plugging ISA cards into a DOS PC and having to select IO Port Number and Interrupt line jumpers. Stacking Arduino shields isn’t exactly as Plug-and-Play simple as plugging in  USB peripherals or PCI boards into a PC. A better solution that scales like USB for Arduinos is needed. Black Mesa Labs has created a simple and low cost solution for this called the “Mesa-Bus”.

[ Introducing the Mesa-Bus from Black Mesa Labs ]

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The “Mesa-Bus” is a simple and completely open text serial protocol designed for transporting self enumerating SPI and I2C bus traffic over a standard UART serial connection. Electrically the interface is simply LVCMOS 3.3V RX and TX serial on a standard FTDI 1×6 6 pin 0.100″ header. Why UART Serial? Every device from PC to Arduino to 8051 has at least one UART serial port. Arduino’s are especially flexible as with Software Serial any unused IO pins may be turned into an additional serial port. The Mesa-Bus is made possible by a custom BML FPGA bridge design that has an autobauding UART, auto-enumeration logic and a SPI/I2C bridge residing in a low cost ICE40 Lattice FPGA. Why use the FTDI 1×6 0.100″ connector? The 3V FTDI 6pin connector is ideal as it is well known, bread board friendly, provides raw 5V for powering modules and has 4 signal pins, 2 Ins and 2 Outs. The Mesa-Bus utilizes all 6 pins for allowing Mesa-Modules to be easily powered and configured either by a Arduino like MCU or a full fledged PC with a $20 FTDI serial cable. Aren’t UART serial connections too slow? The Arduino-Zero example for Mesa-Video development communicates at 3Mbaud over a single wire, considerably faster than I2C and in the ballpark of traditional 4 pin SPI using just 2 pins on the Arduino.

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This small $3 Lattice ICE40LP384 FPGA design below (22x32mm) bridges the “Mesa-Bus” to SPI and allows the EVEy-Video board’s FT813 GPU to interface either to a PC or an Arduino board via the FTDI 1×6 header. The UART sub-component of the FPGA design autobauds to the 1st “\n” character received from the Bus Master and uses that baud rate for upstream ( RDo ) and downstream ( WRo ) communications – allowing Mesa-Bus to scale from high speed 32bit ARM serial ports to simple 9,600 baud bluetooth wireless virtual serial ports. The BML custom Enumerate and Decode Logic inside the FPGA performs bus enumeration so that each device in a Mesa-Bus serial chain is uniquely addressable to the host ( similar to USB enumeration at a high level concept ).  The Bridge Logic bridges the clear text ASCII characters to SPI ( or I2C ) bus cycles specific to the slave device’s requirements on the module. The final Mesa-Video design merges this bridge FPGA design along with the GPU and HDMI converter onto a single board.

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[ PC to Mesa-Bus ]

Why support interfacing Mesa-Bus to a PC that already has USB? Having worked on embedded software+hardware development for 20 years, I have found it tremendously beneficial to be able to prototype embedded software 1st on a PC with a scripting language like Python and then port the software to C for the final embedded MPU. MesaBus is designed to support this development flow.  All Mesa-Video software development was done in rapid prototyping using the Python scripting language on a PC. Once all the initial bringup and custom functions were working on the PC, the software was quickly ported from Python to Arduino C and working stand alone from an Arduino Zero board. This flow is a tremendous productivity enhancer as it avoids the compile, download and repeat loop that often needlessly consumes engineering time developing embedded systems. Prototyping in Python also makes software easily portable to RaspberryPi platforms.MesaVideo(1)

What is the point of “Mesa-Bus” – why not just use SPI natively? “Mesa-Bus” aims to solve both the hardware and software complexity of integrating multiple SPI and I2C peripherals by using any readily available 2-pin serial port and transferring everything in ASCII clear text for easier documentation, development and integration. Binary protocols are more bit efficient, but dealing with clear text protocol transfers is much more human efficient in terms of documentation, development and debug ( think XML versus proprietary binary file formats ).  With Mesa-Bus there are no clocks edges, chip selects or I2C addresses to worry about. All Arduinos have at least one serial port and a virtually unlimited number of Soft Serial ports. MesaBus solves the problem of limited number of available Arduino pins ( think 8-pin ATtiny  ) by allowing for device daisy chaining with built in device enumeration. Mesa-Bus isn’t multi-drop ( like RS485 ), but point-2-point like Token-Ring, electrically superior for performance ( less capacitance, shorter wires ). Multiple MesaBus modules connect to a single Arduino ( or other MCU ) serial port and are uniquely addressed automatically based on their location in the chain. Modules are breadboard friendly with their 0.100″ 1×6 male headers and a 4 slot ( expandable to 8,12,etc ) back plane is on the drawing board for compactly connecting multiple Mesa-Modules in a single serial chain in a 1″ x 2″ form factor.

Back to Mesa-Video – here are the two separate boards joined together.

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The final PCB iteration combines both designs onto a single 1″x3″ (3cm x 8cm) board with no center connectors for the SPI interface.

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[ Video Capabilities ] : Mesa-Video software is a subset of the entire FT813 GPU video capabilities in order to make it quick and easy for novice to expert Arduino developers to display text and limited graphics from their Arduino onto any HDMI ( or DVI ) display. The FT813 GPU is extremely capable, but also complicated and non trivial to get started programming with the entire API from FTDI. Mesa-Video simplifies things by providing a simple UART serial interface on the input and a fixed 800×600 HDMI interface on the output. MesaVideo is intended for displaying real time information ( like live variable status, progress bars, stock quotes, centrifuge status, etc ). Why not just use a RaspberryPi? RPis are great – but they aren’t microcontrollers – they are full fledged Linux workstations with powerup and powerdown requirements ( and memory card corruption issues ) that Arduinos just don’t have to worry about. Mesa-Video fills the niche of when a small Arduino is the right tool for the embedded job ( flying quad-copter?), but a graphic output ( either just for development debug or final product ) is needed.

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Below is an example electrical setup of Arduino ZeroPro + Mesa-Video illustrating the advantage of Mesa-Bus over a conventional SPI interface. There are only 3 wires, +5V, GND and TX ( Pin-1 in Arduino parlance, WRi on Mesa-Bus ) connecting the Arduino to Mesa-Video. Mesa-Video is a write-only interface so the RX serial pin doesn’t need to be hooked up.:

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First “Hello World” Example Sketch for Mesa-Video. There are no include files, this is everything that is needed to bring up the GPU and display basic text at a specified (x,y) location. The hex strings within brackets are actually SPI bus cycles. Encoding the SPI bus cycles in ASCII text makes Mesa-Bus designs portable, easy to document and highly compressible ( as shown ). The low cost FPGA on each Mesa-Module does all the required conversion from ASCII text to SPI ( or I2C ):

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Below is an out of focus picture of the Hello World sketch ( actual text on the LCD looks great – the digital HDMI SVGA signal is perfect ). Basic ( non-painted ) text is available in 1x, 2x or 4x sized VGA fonts:

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[ Whats Next ] :   Next step is to assemble the final board that merges the Mesa-Bus SPI bridge FPGA and the GPU+HDMI onto a single board.  Layout of the merged design is shown below in CopperConnection – a fantastic simple to use and low cost layout tool that exports Gerbers ready for OSH-Park.  CopperConnection is as easy to use as ExpressPCB – but it generates Gerbers that can be fabbed out anywhere. Best $50 I’ve spent in a long time. I’ve since upgraded to the $100 “Ultimate” edition that allows me to generate and hand edit ( via custom Python scripts ) the actual board files. Fantastic Tool – check it out over at RobotRoom  free version doesn’t export Gerbers – but is a nice demo.  Below is the merged Mesa-Video design, it is 1″ x 3″ ( 77 x 26mm ).

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The FPGA has been upgraded from the 400 Logic Cell ICE40LP384 to the new 4,000 Logic Cell ICE5LP4K. The new and larger FPGA is a game changer for BML as it is only a few dollars more and provides 10x the resources, contains 80Kb of SRAM and also an internal 48 MHz oscillator in a 1cm^2 package that is 2-layer friendly.  To simplify design and manufacturing, the single ICE5LP4K device will be used on all Mesa-Modules going forward. The larger FPGA with SRAM supports an alternative bitstream idea that could potentially turn Mesa-Video into a 4-channel LVCMOS digital logic analyzer ( no computer involved ). The power of open-source is that it turns any project like Mesa-Video into a canvas for others to improve upon. Final firmware design will be EEPROM upgradable over the Mesa-Bus interface – supporting in-field FPGA upgrades from any PC with a FTDI cable.

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[ Mesa-Duino-M0 ] : Mesa-Duino ( for short, pictured above – 1st proto ) is an Arduino-M0 compatible derivative that plugs directly into slot-0 of the Mesa-Backplane and becomes the bus master instead of an external board. Total BOM for the assembly is less than $10 – which is pretty impressive for a 48 MHz 32bit ARM CPU with 256KB Flash and 32KB SRAM in a 1″ x 1″ form factor.  The actual Arduino-Zero (.cc) and Arduino-Zero-Pro (.org) contain an Atmel-ICE on-board. The Mesa-Duino design removes the ICE and makes it just the ARM CPU, a FTDI connector for the Mesa-Bus mastering and a micro-USB for firmware upgrades – reducing the BOM item count by like 90% while maintaining compatibility with the Arduino IDE ( ultimate goal – and why ATSAMD21G18 was chosen ).  BML encourages users to use whatever microcontroller they already have for Mesa-Bus mastering – but if you wan’t something really powerful, small and inexpensive – the Mesa-Duino with a 3Mbps hardware serial UART on board is a nice solution. Next board spin will remove the large 2×8 header. If BML can locate someone to manufacture the Mesa-Duino, the intention would be to provide kick back royalties to the Arduino organization for future Arduino development expenses.

[ PCBs also in the queue ] : Along with Mesa-Video, 4 other PCBs have been sent out to fab to begin the Mesa-Module family. All Mesa-Modules heavily reuse the same FPGA layout and are all 1″ wide with identical 1×6 0.100″ right angle header connector for plugging into a FTDI Cable, a Mesa-Backplane or a standard bread board. Cost is very low, with BOM for all below $10.

Mesa-Logic : A general purpose FPGA development board with 4,000 Logic Cells, SRAM on chip and 16 LVCMOS 3.3V IOs ( limited drive strength). The FPGA will be firmware upgradable in the field allowing users to design whatever.

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Mesa-GPIO : A general purpose IO module with 16 3V 25mA drivers, 5V tolerant via a PCA9539 IO Port Expander IC. 1.5″x1″ (38x26mm). Mesa-GPIO is a typical example of a low cost Mesa-Module, left 1/2 of the PCB is the Mesa-Bus 1×6 connector and the bridge FPGA, right 1/2 of the PCB is the IC specific to the module and user connector for that IC.

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Mesa-ICT : Pogo-pin board for programming FPGA EEPROMs post assembly. 1.2″ x 1″ (30x26mm). The header on the right mates either to the Lattice HW-USBN-2B programmer or the Mesa-Logic module for rapid “self-hosting” EEPROM programming post assembly as a bed-of-nails test fixture. Eight 0.050″ pogo pins hold off FPGA configuration and provide full access to EEPROM for external programming.

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Mesa-Backplane : 4 slot back plane that may be cascaded for more slots. 1.3″x0.7″ (33x18mm). Mesa-Bus connections are point-2-point ( WRo to WRi and RDo to RDi ), meaning that cascade depth is limited by the 5V supply current, not the number of loads on the serial bus. Multiple backplanes connect end to end to support 4,8,12, etc modules from a single master.

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The 5 boards have been sent out to fab and should arrive around mid September 2015. The ICE5LP4K FPGAs in the 2-layer friendly SG48 QFN 0.5mm pitch package are newly released from Lattice and a reel of 50 have been special ordered from Digikey that are due to arrive 1st week of October. Plan is to hopefully acquire some more ES GPUs from FTDI and begin assembling 3 boards of each design to send out for evaluation by interested parties for potential volume manufacturing.

[ Mesa-Modules ]

All Mesa-Modules will be fixed 1″ wide and length available to grow as needed for each design. Most Mesa-Modules will be 1″x1″ with a BOM cost of under $10 for things like GPIO, H-Bridge, Stepper Motor Controller, RTC, thermal sensor, etc . Converting an existing breakout board design from places like Adafruit and Sparkfun to a Mesa-Module should be easy and only be a $5 adder for the Mesa-Bus bridge FPGA and some BML engineering time.

mesa_video

The Mesa-Video design with 3 ICs ( not counting LDOs ) should have a total BOM cost at around $20-$30. The retail cost would need to stay below $50, which should be possible. Mesa-Bus is a solid and easy to use solution for expanding Arduinos with USB like simplicity. Please reply to this post and write to me what you think and what kind of Mesa-Modules you would like to see.

faq

[ Mesa-Video FAQ ]Intel_P8051

o Does Mesa-Video work with devices other than Arduinos? Yes, it will work with any device with a 3.3V LVCMOS ( or level shifted to ) UART serial port.  Got a Teensy, Intel Edison, or even an old 8051 design that you would like to add video to? Bring it on. The bus master sets the bit rate for all devices. This hasn’t been tried yet, but the Mesa-Bus protocol is asynchronous and clear-text, designed to be portable so it should work great over a wireless Bluetooth serial link like a BlueSmirf. With a wireless link it should be possible to use Mesa-Video as a wireless remote display from a desktop PC or Arduino to a TV ( think home security monitoring, stock tickers, etc ), or place the Arduino in a quad-copter and have it stream live video over bluetooth (or other wireless standard) to a remote Mesa-Video display. Clear text protocols like Mesa-Bus are very portable. Designed around old school ( and versatile ) UART serial communications of a wide baud range, it is very simple to convert from LVCMOS 3.3V serial to RS-232 (single-ended) or RS-422 ( differential ) for long runs of to 1,500 meters ( almost a mile for Luddites like me ). SPI and I2C just aren’t designed for this.

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o How difficult is the software to integrate into my design? The complexity of the software depends on how many features you intend to use. BlackMesaLabs provides the basic Level-1 ( Text Only ) and Level-2 ( Text + Limited Graphics ) software in both Arduino C++ Sketch and Python for PC examples. Level-3 software is the full up FTDI development kit available here and makes all of powerful FT813 features available. If all you want is to display some debug text information, my screen shot of the Arduino-IDE is all the software that is required.

o What are the Level-1 text modes? When the display is initialized, 1of3 VGA text display modes may be selected. 1x Zoom for 98×36, 2x Zoom for 49×18 or 4x Zoom for 24×9. The graphic text provided by the FT813 can mix and max varying font sizes.

o What are the Level-1 functions? video_setup(), clear_screen(), clear_console(), print_at() and print_ln(). The function print_at() displays a text string at specified x,y location on the screen. The function print_ln() appends and scrolls a text string on a virtual console.

o What will the Level-2 functions be? Most likely draw_text(), draw_point(), draw_line(), draw_rectangle().

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o If Mesa-Bus and Mesa-Video are open-source software and hardware, where are all the design files? All of the design files are safely stored on the Black Mesa NAS. Once a relationship between BML and a board assembler and distributor is established, the appropriate time and location to upload all design files to the internet ( most likely GitHub ) will be determined.

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o What is the maximum bit rate of Mesa-Bus? It has been tested at 3Mbps, which is the maximum UART rate of the Arduino M0 hardware. Final FPGA bridge design will be clocked at 48 MHz, which assuming 8x asynchronous serial oversampling, a baud rate of 6Mbps should be possible. FPGA to FPGA serial communication where both FPGAs have the same 48 MHz base clock could potentially work at 4x oversampling, or 12 Mbps. One Mesa-Module idea BML is considering ( which may seem ludicrous on the surface ) is a bitstream for the Mesa-Logic board called Mesa-UART, a FPGA design that would take SPI from a CPU ( at say 20 Mbps ) in SPI binary format and stuff the traffic into a rate converting FIFO which is then serialized using a fast UART for Mesa-Bus mastering at 12 Mbps. This may seem like a lot of work ( and overhead ), but for uCs with slow UART serial ports – this is a viable solution for fast data transfers. Mesa-Logic is very flexible and fully open-source FPGA design meaning that a user specific project could easily be adapted requiring only a new FPGA bit stream ( for example, an 8bit parallel interface with IO strobes from an Apple ][ – level shifted from 5V to 3V of course ).

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o May SPI be used instead of Mesa-Bus UART serial protocol with Mesa-Video? Yes, on the final design the bridge FPGA will have a bypass pin that may be tied to GND. This will bypass the FPGA’s UART and Mesa-Bus decoder and pass SPI signals from the FTDI 6 pin connector to the SPI interface of the FT813. In this configuration, the SPI setup and hold timing will vary slightly from the FT813 spec and the FTDI 1×6 connector will no longer be compatible with a FTDI cable or a Mesa-Backplane. This SPI bypass option is an excellent development interface for someone ultimately targeting a FTDI Flat Panel Module ( See Below ) for a commercial application:

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o Why Buy Mesa-Video when a 512×512 FTDI 5″ Flat Panel is available for $100? Primary difference is that Mesa-Video drives large displays at 800×600 resolution and simplifies digital video from any Arduino sketch without requiring importing a mountain of libraries and understanding the GPUs programming interface. The EVE FT800 series of chips are very powerful – which also means complicated – even just for basic things. Mesa-Video makes the simple things simple without giving up the full power of the FT813. The full FTDI EVE API is still available to use with Mesa-Video hardware.

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o Will a version of Mesa-Video that supports gaming be made available? Excellent question, this FT813 design actually canceled the original BML GPU design called Video-Duino as the FT813 is much smaller and more cost effective than the Spartan6 FPGA based GPU. The FT813 is a fantastic, small and low cost solution for displaying text and primarily static graphics. If there is enough interest, the FPGA GPU design may be restarted using a Lattice ICE5LP4K  FPGA ( low cost and small like the FT813 ). This would either be designed like a 3DFX like graphics accelerator , a GPU that goes between the FT813 GPU and HDMI chip and overlays real time gaming graphics, or possibly standalone FPGA GPU.  Idea is for the design to provide 8×8 Bitmap Textures and Sprites with velocity and collision detection integrated into the FPGA hardware design ( offloading Arduino of real time work ). It would be a fun development platform for 8bit NES like 2D video gaming. Color resolution may need to be reduced from 24bit to 9bit for a small low cost FPGA to handle the interface. Please respond if there is any interest out there for a gaming specific module like this.

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o Is this an Arduino shield ( shown above )? No, but it could potentially replace the shield concept as a much simpler, smaller and more robust method for adding multiple peripheral devices to an Arduino. A Mesa-Bus back plane is in the queue that supports 4 slots ( and can cascade to 8,12, etc slots ) and there is also an Arduino Zero compatible Mesa-Zero module. There are multiple low cost Mesa-Modules envisioned, Mesa-Video just happens to be the first.

o Do multiple Mesa-Modules have to be daisy-chained? No, if you are concerned about latency or series circuit aspect – the CPU master may use a separate serial port pair for each Mesa-Module. Arduino’s Software-Serial makes this very easy.

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o Is Mesa-Video Low Power? Yes! No promises of powering Mesa-Video  from a single lemon, but using this handy USB Current Meter that measures 5V USB Current in 10mA units, on powerup, with HDMI disabled, it measures current at 0 (so less than 10mA ) and with everything enabled generating video at 800×600 it measures 40mA ( so less than 50mA – Take that nVidia! ). Power-on inrush current has not yet been measured yet. USB 2.0 is rated for 500mA, so a person could theoretically drive 10 HDMI video displays from a single PC over a FTDI cable using 10 Mesa-Video boards daisy chained on a Mesa-Backplane ( think 60″ LCD TVs in a giant 3×3 15’x15′ array…. ). The 0.100″ +5V pin on a 1×6 header is physically rated for 3 Amperes, so the Mesa-Bus has room to grow.

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o What is the Mesa-Video resolution and timing and may it be changed? The open-source software for Mesa-Video automatically configures the hardware for 800×600 56 Hz timing per VESA Spec VG900601.  This was selected as the FT813 PLL is able to exactly generate the 36 MHz dot clock for 800×600 and 36 MHz exceeds the 25.175 MHz DVI minimum. The FT813 chip itself may be configured for other frequencies, but this falls outside the scope of Mesa-Video hardware+software. Plug fest tests thus far have shown that computer displays with DVI or HDMI inputs agree and work well with 800×600 input feed regardless of their native resolution and aspect ratio.

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o What else is Mesa-Bus good for besides Arduino expansion? Remember the days of the LPT1 parallel port when it was easy to add homegrown bread boarded hardware to a PC? A Mesa-GPIO module can bring those days back. A $20 FTDI cable plus a similarly low cost Mesa-GPIO board with a PCA9539 provides 16 5V tolerant IO pins the PC can interface using any language that can talk to a standard COM serial Port ( Perl, Python, Powershell, etc ). Need more than 16 IOs? Buy a Mesa-Backplane and populate it with 2 or more Mesa-GPIO modules.

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o What other Mesa-Modules from BML are planned? Here is the complete list to date:

  • Mesa-Video : 800×600 HDMI/DVI Digital Video.
  • Mesa-Backplane : 4 slots for Mesa-Modules. Cascadable.
  • Mesa-GPIO : PCA9539APW based 16 3V 25mA GPIO pins ( 5V Tolerant ).
  • Mesa-Analog : AD5592 8 Channel 12bit ADC/DAC/GPIO.
  • Mesa-Stepper : L6470H based Stepper Motor Controller.
  • Mesa-Relay : ULN2803A Darlington based 500mA inductive load driver.
  • Mesa-Logic : Lattice ICE5LP4K based 4K LUT FPGA fabric with user IO.
  • Mesa-DeadBug : Plugs into Mesa-Logic for dead-bugging any IC to 16 IOs.
  • Mesa-Memory : 8Mb Flash, 1Mbit SRAM and 16Kb FRAM ( non-volatile ).
  • Mesa-Environment : Temp, Light, Accelerometer, Altimeter, Magnetometer.
  • Mesa-Time : RTC clock and programmable timers.
  • Mesa-Touch : 11 pin capacitive touch sensor ( AT42QT1111 ).
  • Mesa-UART : 6 Mbps SPI to UART bridge for CPUs with slow UARTs.
  • Mesa-Duino : Arduino M0 derived bus master ( 48 MHz 32bit ARM CPU ).
  • Mesa-ProMini : Arduino ProMini bus master ( 8 MHz 8bit AVR CPU ).

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Please reply if you know which Mesa-Modules you find most interesting or if you think of something missing. My direct email is available at the very end of the BML Welcome Page. The BML goal is to reuse the same FPGA bridge design and crank out multiple modules.  FPGA reuse greatly simplifies design effort, production assembly, test and firmware programming. Goal is for the Mesa-Modules to retail in the $20 – $40 range, just slightly more expensive than a basic SPI or I2C breakout board. The two CPU boards aren’t required of course ( any board with a serial port will work ), but will be much smaller ( 1″x1″ ) and less expensive than conventional Arduino boards as they won’t have IO ( only the 6 pin Mesa-Bus ). The picture above is the Mesa-Zero proto ( final version won’t have the 2×8 connector on right ).

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Something very similar to this Intel Edison UART adapter ( shown above ) with RX and TX swapped would make for a great Mesa bus master too. Edison isn’t really my bailiwick, but would be a great solution for a project needing Wifi or Bluetooth built in. The clear text UART serial protocol of Mesa-Bus makes it simple to switch CPU architectures.

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Electrically, RaspPi would work too – Mesa-Video might not make much sense, but the other Mesa-Modules can dramatically increase ( and isolate ) the IO capabilities of a standard RaspPi.VintageRadioShack_Storefront

o Where can Mesa-Video be purchased? Excellent question.  Sadly, probably not at your local Radio-Shack. Goal is for Mesa-Video to be  a completely open-source hardware and software ( like Arduino ), low cost and readily available in volume for all Arduino developers yearning for a video display. Mesa-Video ( along with other Mesa-Modules ) can greatly accelerate the Maker-Movement by making it much easier for artists to implement their Arduino based designs. BML only does initial prototype assembly and is therefore  actively looking for a production manufacturer and distributor such as Sparkfun , DangerousPrototypes, SeeedStudio or Adafruit that might be interested in Mesa-Video and other planned family of Mesa-Modules. The FT813 GPU chip is not available for purchase just yet, so this design is still in pre-production evaluation until October-2015. Please provide feedback and express any interest in a Mesa-Video board and the Mesa-Module family. Black Mesa Labs aims to assist the Maker Movement by Delivering the Future … 2 Layers at a time.

theend

Mesa-Video : 800×600 Digital video for Arduinos over 2-wire serial Mesa-Bus

Arduino Pro Mini x4 PCB arrived from OSH-Park

[ 01.11.2015 ] : My latest Arduino design arrived in yesterday’s mail. This design is made to be compatible with the Sparkfun Arduino ProMini so that the standard Arduino IDE will have built in recognition to my board. My twist on the design is that it is REALLY small 12mm x 23mm ( about 0.5″ x 1″ so it only cost me $2 to make ). The only external interfaces are a Nano x4 connection to my FPGA family containing the Arduino SPI interface and a FTDI UART interface for Arduino configuration. The board is too narrow for a standard 1×6 FTDI cable connection, so I instead pinned it out as a 2×3 connector and then designed a 2×3 to 1×6 adapter board.

Purpose for this board is that if I ever need one of my Nano FPGA boards to do any kind of complex sequencing or report generation,etc that is too involved for a hardware FSM and would be better suited to a CPU, I could plug an Arduino into my FPGA and interface via 4-wire SPI over a Nano x4 bus connection.  Xilinx has their inferrable Powerblaze CPU core – but its a huge hassle to design one in and get the tool chain all up and running ( plus $ ).  Arduino is very simple in comparison.  Other nice thing is the AVR chip of an Arduino has all the Flash and SRAM built in leaving all the FPGA resource available for the real hard lifting.

I may or may not assemble this right away.  This is actually my 2nd version of this board, 1st was done prior to the Nano bus standard and was a DIP mounted board and used the MLF package instead of QFP. Bringup takes a bit of doing. Unfortunately, “Arduino” doesn’t use the built in Atmel bootloader ( which is SPI based ) but instead uses an Arduino bootloader that you have to get in the 8bit Atmel CPU before it is an Arduino and not just an Atmel AVR.  This process involves using an Atmel USB dongle to configure the AVR clock setting, and then using an Actual Arduino to load the Arduino bootloader into the AVR over SPI.  Thankfully I wrote the entire process down a year ago.  At the end of the day, I end up with an Arduino board that plugs into my FPGAs and can accept compiled C code to tell my FPGAs to do something.  Unfortunately, at the end of the day – do I really want to write and compile C code? Been there, done that, no – not really. I think my RaspberryPi project ( with interpreted Python ) is really where I want to write code for most designs. The Arduino I might just stick in my back pocket for when I need something software driven that must be REALLY small and REALLY low power ( outside of RaspberryPi space ).

[ Arduino Pro Mini x4 ]

[ FTDI Adapter 2×3 to 1×6 ]

Arduino Pro Mini x4 PCB arrived from OSH-Park