BML GPIO-14 USB Board for PCs

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2018.03.18 : BML project for using a $2 FTDI FT260Q for adding 14 bits of GPIO to any PC via USB with no device drivers required.

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Ever miss the simple days of using a PC’s LPT1 parallel port to bit-bang GPIO over 8 output pins and 4 input pins of the DB-25 connector? I sure do.  My first design project as a BSEE graduate in 1993 was to design a LPT1 controlled test fixture for the Motorola MDT-9100-T data terminal (shown below).  Those were the days. By multiplexing 12 parallel port pins into 74HC dip CMOS latches and transceivers my test jig tested all the IO signals of the MDT-9100s 386sx motherboard. All of the diagnostic software could be written in C on my Windows 3.1 desktop thanx to this versatile interface. Those were the glorious simple days of computing.  Sigh…. Then USB came along and killed the wonderfully easy parallel port interface.

But wait, FTDI has recently introduced a low cost and very versatile USB chip called the FT260Q. It is unique in that it requires no device drivers. It provides up to 14 IO pins that can be used for driving LEDs, reading switches, interfacing to LVCMOS circuits all while requiring very little support circuitry.  This open source Black Mesa Labs’ project  describes the DIP-18 breakout board for the FT260Q which may be built for under $5.

 

 

 

The 24 x 19 mm 2-layer PCB may be ordered here from OSH-Park for just about $3 for 3 PCBs.

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[ Bill of Materials ]

Qty-1 : 768-1268-ND : FT260Q-T IC USB TO UART/I2C 28WQFN : $1.83
Qty-1 : 240-2390-1-ND : FERRITE BEAD 600 OHM 0805 : $0.11
Qty-1 : 609-4613-1-ND : CONN USB MICRO B RECPT SMT R/A : $0.42
Qty-2 : F4239CT-ND : TVS DIODE 24VWM 150VC 0603 : $0.65
Qty-3 : 445-4112-1-ND : CAP CER 10UF 6.3V X5R 0603 : $0.06
Qty-2 : 399-7918-1-ND : CAP CER 47PF 50V C0G/NP0 0603 : $0.10
Qty-3 : 445-5111-6-ND : CAP CER 0.1UF 25V X7R 0603 : $0.10
Qty-4 : Resistor 4.7K 5% 0603
Qty-2 : Resistor 33 ohms  5% 0603
Qty-1 : Resistor 1 Mohm  5% 0603

 

Software:

The FT260 is a USB device which supports I²C and UART communication
through the standard USB HID interface. This is very cool as it means it should work with any USB host platform without requiring any special device drivers. See the FTDI Application Note AN_394 User Guide for FT260 for details on programming the FT260Q, also the datasheet.

To send and receive HID reports from Windows ( or Linux ) in the Python environment, the module hidapi is needed. Download the appropriate hidapi Python WHL for your platform from this link  https://pypi.python.org/pypi/hidapi/0.7.99.post21 .  For example, at BML, currently running Python35 on 64bit Windows10, so downloaded both hidapi-0.7.99.post21-cp35-cp35m-win_amd64.whl and hidapi-0.7.99.post21-cp35-cp35m-win32.whl .

  1. Upgrade pip via “python -m pip install –upgrade pip”
  2. Install WHL via “pip.exe install hidapi-0.7.99.post21-cp35-cp35m-win32.whl”

With hidapi installed, you should now be able to run this example script from BML that will configure all the FT260Q pins as GPIO outputs and toggle them as fast as possible.  Note the USB HIDAPI interface to HID-Class devices isn’t “bare metal” blazing fast. This sample Python toggles all the GPIO pins every 300-400uS, or about 1kHz. For Windows, the HID API interface requires all reports be 64 bytes in length, so the example Python here always pads reports with trailing 0x00’s to be exactly 64 bytes long. Untested, but padding the reports under Linux should not be required and may be considerably faster than Windows.

[ ft260q_toggle.py ]

import hid;

h = hid.device();# See https://github.com/signal11/hidapi/blob/master/hidtest/hidtest.cpp
h.open(0x0403, 0x6030) # FTDI FT260Q device ID
h.set_nonblocking(1);

print("System Status");
rts = h.get_feature_report( report_num = 0xA1, max_length = 255 );
print( [ "%02x" % (each) for each in rts ]);# list comprehension
h.send_feature_report([0xA1,0x02]+[0x00] +[0x00]*61 );# GPIO ON, I2C OFF
h.send_feature_report([0xA1,0x03]+[0x00] +[0x00]*61 );# GPIO ON, UART OFF
h.send_feature_report([0xA1,0x05]+[0x00] +[0x00]*61 );# GPIO3 ON, Int OFF
h.send_feature_report([0xA1,0x06]+[0x00] +[0x00]*61 );# GPIO2 ON
h.send_feature_report([0xA1,0x07]+[0x00] +[0x00]*61 );# GPIO4,5 ON 
h.send_feature_report([0xA1,0x08]+[0x00] +[0x00]*61 );# GPIOA ON 
h.send_feature_report([0xA1,0x09]+[0x00] +[0x00]*61 );# GPIOG ON 
h.send_feature_report([0xA1,0x41]+[0x00]*8+[0x00]*54 );# GPIOE,H

# 0xB0 : GPIO Write/Read Request 
# Byte-0 : 0xB0
# Byte-1 : GPIO[5:0] Value
# Byte-2 : GPIO[5:0] Direction 0=Input 1=Output
# Byte-3 : GPIO[H:A] Value
# Byte-4 : GPIO[H:A] Direction 0=Input 1=Output

# Output Loop : Configure all 14 GPIOs as Outputs and toggle them
while ( True ):
    h.send_feature_report( [0xB0, 0xFF, 0xFF, 0xFF, 0xFF ]+[0x00]*59);# Toggle
    h.send_feature_report( [0xB0, 0x00, 0xFF, 0x00, 0xFF ]+[0x00]*59);# All GPIO pins

# Input Loop : Configure all 14 GPIOs as Inputs
h.send_feature_report( [0xB0, 0x00, 0x00, 0x00, 0x00 ]+[0x00]*59);
while ( False ):
    rts = h.get_feature_report( report_num = 0xB0, max_length = 255 );
    print( [ "%02x" % (each) for each in rts[0:6] ]);# list comprehension
h.close();

[ GPIO Pin Power Up Defaults ]

Not all pins powerup in GPIO tri-state mode. If powerup condition is important, BML recommends using the non-tristate pins as inputs with series resistors between your circuit and the FT260Q.  The tristate pins you should be able to pull high or low on powerup with appropriate (1K) resistor.

0 - Hard Low
1 - Tristate
2 - Tristate 
3 - Tristate - pulled up
4 - Hard High
5 - Tristate
6 - Tristate

7 - Hard Low
8 - Tristate
9 - Tristate
10 - Tristate
11 - Tristate
12 - Hard Low
13 - Tristate

[ Future Plans ]

Black Mesa Labs has plans to use this IC as both a SPI PROM programmer and UART interface to future FPGA boards. The low cost, small size and minimal external components ( no crystal, PROM, etc ) make this an ideal IC for low cost educational FPGA development boards from Black Mesa Labs. Next tutorial on using the FT260Q will make use of the internal UART capable of 12Mbaud. Look for future Xilinx Spartan7 boards from BML with a FT260Q embedded for both PROM programming of a bootloader and UART interface for Mesa Bus transfers at 12Mbaud.

[ EOT ]

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BML GPIO-14 USB Board for PCs

BML USB 3.0 FPGA interface over PMOD

2017.12.19 :  Black Mesa Labs is presenting an open-source-hardware USB 3.0 to FPGA PMOD interface design.  First off, please lower your expectations. USB 3.0 physical layer is capable of 5 Gbps, or 640 MBytes/Sec. This project can’t provide that to your FPGA over 2 PMOD connectors – not even close. It does substantially improve PC to FPGA bandwidth however, 30x for Writes and 100x for Reads compared to a standard FTDI cable based on the FT232 ( ala RS232 like UART interface at 921,600 baud ). A standard FTDI cable is $20 and the FT600 chip is less than $10, so BML deemed it a project worth pursuing.

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Measured Data Transfers comparing FT600 to FT232:

USB 3.0 to FT600 at 100 MHz: Writes=1,384 KBytes/Sec, Reads=567 KBytes/Sec

USB 3.0 to HUB to FT600 at 100 MHz: Writes=416 KBytes/Sec, Reads=187 KBytes/Sec

USB 2.0 to FT600 at 100 MHz: Writes=279 KBytes/Sec, Reads=131 KBytes/Sec

USB 2.0 to FT232 1×6 0.100″ at 1 Mbps: Writes=43 KBytes/Sec, Reads=5 KBytes/Sec

Wait, what?  Measured in KBytes not MBytes per second? Is BML to blame? Only partly. This BML project utilizes 1/4 of the LVCMOS bandwidth possible of the FT600 to both make the IO fit across PMODs and also work with existing Mesa Bus Protocol IP.  The FT600 has 16 data pins capable of 200 MBytes/Sec but 1/2 the data pins are deliberately tossed to fit within 2 PMODs ( 3 PMODs wouldn’t be practical ).  Existing Mesa Bus Protocol IP is used – which transfers ASCII nibbles (0-9,A-F) instead of binary, so the maximum logical throughput is reduced another 2x to 50 MBytes/Sec.  Observed transfers are just over 1 MByte/Sec.  This means if all 16 pins were used and a binary protocol transfer instead of ASCII, rate would be about 5MBytes/Sec – still away off from 200 MB/s . So what is going on? This is a perfect application for the SUMP2 Logic Analyzer from BML.  Instead of wiring up the iceStick, SUMP2 was instantiated directly in the FPGA along with the FT600 interface ( this is really what SUMP2 is designed for, a free open-source replacement for Xilinx ChipScope and Altera SignalTap. SUMP2 supports capturing 32 compressed events and up to 16 non-compressed DWORDs into on-chip FPGA block RAM ). Below is a PNG screen dump of SUMP2 capturing the FT600 FIFO status flags (RXF,TXE) and the FPGAs control signals ( RD,WR ). What is immediately apparent is that the majority of the time ( ~154uS out of ~160uS ) the FT600 doesn’t have any data for the FPGA. RXF is sitting low even though Python is trying to send data as fast as possible.

sump2_0009.png

Within a 10 ns clock cycle of RXF asserting, the FPGA asserts RD and converts the Mesa Bus Packet into a local bus burst ( with about 350ns of pipeline latency ). The observed distance between the 32bit lb_wr pulses is precisely 8 clocks, the fastest possible ( DWORD = 4 Bytes x 2 ASCII Bytes per Binary Byte = 8 clocks ).  Clearly both the FT600 and the FPGA design are working as fast as possible with what is coming down the USB 3 pipe.sump2_0010.png

So, the truth is that the majority of the time ( 154/160us = 96% ) the PMOD interface is sitting idle even though Python is trying to write and read from the FT600 as fast as it can. Clearly the USB 3.0 pipe is not full. Who is to blame? Is it Python? Windows? Intel Chipset? Don’t know. Would it be faster on Linux? Hopefully. Would compiled C be faster than Python? Probably. Would we ever achieve 50 MBytes/Sec? Probably not. FTDI Application Note AN_386 goes into some detail, there is a lot of software between the user software and when the electrons finally hit the USB 3.0 cable.

Is just over 1MBytes/Sec a disappointment? Yes.  A show stopper? No. Using the FT600 is still the fastest way (BML is aware) of inexpensively getting data from a PC into any FPGA without instantiating a PCI Express IP core and building a PCI Expresss plug in card. 30x and 100x improvements on Writes and Reads is substantial.

2017.12.20 – Update, an acquaintance on Twitter has reported using an FT600 with a proper C client over an FMC connector (all 16 pins, 100 MHz,  binary transfers ) of 185 MB/s ( out of 200 MB/s total ). That is excellent news and proof that Python is most likely the bottleneck. Based on his results, the BML dual-PMOD board should be capable of 1/4 that ( 8bit, ASCII ) or 46 MB/s. Github link to C source is here.

2017.12.21 – Update – another acquaintance on Twitter has reported achieving 240 MB/s using FT601 ( 32bit ) and C on Linux. His USB interface software is on Github here.

Now that performance explained – About the design, let’s begin:

[ Software Setup ]

Step-1) Download and install FTD3XX Device Driver from FTDIchip.com .  For example, for Windows, download and run FTD3XXDriver_WHQLCertified_v1.2.0.6_Installer.exe

Step-2) Download and install Python module for D3XX from FTDIchip.com.  For example, unzip D3XXPython_Release1.0.zip, “%cd D3XXPython_Release1.0” and then “%python setup.py install”

Step-3) Create a directory for your script and copy FTD3XX.dll and FTD3XX.lib from unzipped D3XXPython_Release1.0 folder.

[ Hardware Setup ]

Board design.  The board is a 2-layer PCB that is available either via Gerber download or direct purchase from OSH-Park here ($10 for Qty-3). The board consists of the FT600 chip from FTDI, 3 LDO regulators, a 30 MHz crystal and a bunch of 0603 and 0805 passives ( 10uF, 0.1uF, 18pF, 10K, 1.6K, 33 ohm, Ferrite Bead ).

bml_ftdi_usb3_to_pmod

FPGA Hardware setup is a bunch of Verilog IP.  I/O timing over the PMODs was tight, so a PLL is used to remove clock tree insertion delay on the 66/100 MHz clock provided by the FT600. Xilinx Spartan3 LVCMOS 3.3V 8mA Fast IO buffers were required to run at 100 MHz. Since actual throughput doesn’t really get impacted, it is recommended to run at 66 MHz unless a 100 MHz clock is needed for other reasons. The clock from the FT600 is software selectable to be either 66 MHz or 100 MHz and the clock automatically shuts off when USB sleeps during inactivity. Thankfully, it turns on 100’s of ms prior to data transfers, allowing for PLLs to lock if needed.  WARNING: An annoying feature of the FT600 is that using the FTDI configuration program you can select to keep the FT600 clock on always – but what isn’t mentioned is that if you select this option, the device will no longer work with USB 2.0 – at all.

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Design files are here on my public dropbox. They include example Python for testing Write/Read performance, Bill of Materials, Gerbers, Layout files, Layout Screen Shots and example Verilog test design working on a Xilinx Spartan3. A future blog post will go into details on using Mesa Bus Protocol for virtual 32bit PCI like register reads and writes both from user Python and with bd_shell.exe – a Windows .NET app written in Powershell that provides a useful command line interface for writing, reading and scripting register access over a Mesa Bus Protocol link ( either FT600 dual-PMOD or simple FT232 2-wire. A new version of bd_server.py here supports both FT232 and FT600 interfaces for applications like sump2.py and bd_shell.exe to share access to FPGA memory space using Mesa Bus Protocol over Berkeley Sockets for ICP. SUMP2 works great over the FT600, especially for captures with 16 DWORDs of data at 8K samples – the 100x faster reads makes a huge difference.

Stay tuned for more BML open-source hardware and software projects that utilize this FT600 USB 3.0 interface.  Follow me on twitter @bml_khubbard

[EOF]

 

BML USB 3.0 FPGA interface over PMOD

BML DVI digital video for FPGAs over PMOD

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2018.11.18 : Update – new board added. Does full 24bit color video using DDR instead of SDR.  Board fab may be purchased from OSH-Park here.

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2017.12.15 :  Black Mesa Labs is proud to present two open-source-hardware DVI  video boards for adding TMDS digital video to FPGA platforms with standard PMOD connectors.  These two boards are currently available to purchase as bare fabs directly from OSH-Park, or Gerbers and design files may be downloaded from BML here.

——————————————————–

BML 3bit DVI over single-PMOD:

bml_3b_hdmi_top_and_bottom.PNG

The BML 3bit DVI over single-PMOD uses 7 of 8 available LVCMOS 3.3 pins on a single PMOD to provide 3bit color ( R,G,B 100% On or Off ). Example Verilog design drives 800×600 using a 40 MHz dot clock. The TI TFP410 is very versatile in the resolutions it can generate and is really just limited by the clock that the FPGA can provide and the data rates the PMOD connectors are capable of. The bare 2-layer fab may be purchased from OSH-Park directly for $5 USD ( for 3 boards ) from this link. The TFP410 is about $8 USD. The IC and this HDMI Connector is pretty much the BOM, so the entire cost to assemble is less than $20 USD. The rest of the BOM is Qty-2 0603 0.1uF Caps ( 25V 20% X7Rs were used ), Qty-1 0603 10uF Cap, Qty-1 0805 500ohm 1% resistor and an optional 0805 Ferrite Bead ( 240-2390-1-ND was used, but may be replaced with a wire ).  If you don’t want to power the TFP410 from your FPGA’s 3V rail, the Ferrite Bead may be removed and a BU33 ( or equivalent 5SSOP) 3.3V LDO regulator and 10uF cap may be stuffed and the board may be powered by a 5V input via.

The 3bit color Test Pattern from the board driven by FPGA sample design looks like this:IMG_2530.JPG

Note that blue exists, it is just off screen.  With 3bits of color you get 8 colors by additive color mixing  for Black, White, Red, Green, Blue,  Yellow, Cyan, Magenta.

Below is a picture of the 3b board plugged into a Lattice ICE40 icoBoard which is available from Trenz here.  The smaller iceZero board (PiZero dimensions), also a Lattice ICE40 is a joint BML and Trenz design and would also be a good platform for DVI video and is available here.

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Design files for the board, including Gerbers, BOM and text netlist description may be downloaded from my public Dropbox here.

——————————————————–

BML 12bit DVI over dual-PMOD:
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The BML 12bit DVI over dual-PMOD uses 16 of 16 available LVCMOS 3.3 pins on two PMODs spaced 0.900″ center-to-center per Digilent spec. The 12bit color provides 16 shades each for Red, Green and Blue. Example Verilog design drives 800×600 using a 40 MHz dot clock.  The bare 2-layer fab may be purchased from OSH-Park directly for $11 USD ( for 3 boards ) from this link. BOM is identical to the 3b version, just another PMOD 2×6 right-angle 0.100″ female connector is added. Test Pattern video from the board looks like this ( blue is off screen ):

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Example Verilog.  The open-source example Verilog here was used to generate the test patterns shown from a Xilinx Spartan3 board. The design itself is very portable and only requires the FPGA to have a 40 MHz clock and the ability to mirror the clock out to the TFP410 IC using a ODDR or equivalent DDR clock mirroring and the IO ring.  If IO timing for your particular FPGA board doesn’t work, often it may be tweaked to work by adjusting the drive strength and slew rates of the clock out relative to the data out.  Note: BML deliberately chose NOT to use the built-in DDR capability of the TFP410 due to wide variability of I/O timing from various FPGA boards over PMOD interfaces.  SDR is most likely to work across platforms so it was chosen.

A word about video timing – it is tricky. The TFP410 will generate just about any timing you throw at it, but your monitor ( or TV ) might not like it. This on-line calculator is extremely helpful in calculating all the Sync Widths, Front Porch, Back Porch timing parameters. Provided with a resolution ( 800×600 for example ) it will spit out the Verilog def_h_total and def_v_total times ( 1000×667 at 40 MHz for 60 Hz for example ) and the blanking times ( Hsync and Vsync widths, 56 and 3 for example for def_h_sync, def_v_sync ). The porch numbers are then whatever is left over. For example 1000-800-56 = 144. 144/2 = 72 which should work for def_h_fp ( Front Porch ) and def_h_bp ( Back Porch ). It takes patience and experimentation to generate something your monitor is happy with. If your display locks, but isn’t centered, then your porch numbers need to be adjusted accordingly.

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BML hopes that you enjoy these free and open-source board designs for adding DVI video to FPGAs. Check back soon for posting on new USB 3.0 to PMOD adapter using FTDI FT600 FIFO Chip.

2017.12.19 : Updated to fix Gerbers for 3b version with incorrect soldermask on video connector.

[EOF]

BML DVI digital video for FPGAs over PMOD

SUMP2 – 96 MSPS Logic Analyzer for $22

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2016.22.22 : SUMP2 now also available for RaspPi+icoBoard here.

2016.12.13 : Great video on SUMP2 from Bil Herd at Hackaday.

2016.10.31: Thanx to SteveDC, a 3D printed case is now available for SUMP2 here.

2016.10.30 : SUMP2 5V Input shield is now available from OSH-Park for $5. BML can also design similar shields for RS232,RS422/485,LVDS and CAN Bus if there is any interest.

2016.10.24 : Black Mesa Labs has an ongoing mission to develop easy to use and fully capable open-source hardware and software tools that make engineering electronics easier. One such tool is this new low cost open-source logic analyzer called SUMP2 for people who otherwise work in the blind without an oscilloscope or logic analyzer on their bench top.  BML’s 1st incarnation called SUMP1-RLE in 2014 was a 16bit FPGA based logic analyzer that performed real-time hardware compression and decompression. The decompressed data was streamed out over USB using the open SUMP protocol ( hence the name ), allowing it to be used with the excellent Java software from the original 2007 sump.org project. The SUMP1-RLE project was later enhanced from just 16 triggerable events to also include 2 DWORDs of “data” ( additional 64bits of non-triggering non-compressed signals ) and advanced triggering options. Including the data DWORDs made SUMP1 a useful tool for complex FPGA development debugging of internal FPGA event nodes and data paths. These new features required new custom software, written by BML in .NET for Windows. The software was functional, but graphically slow and was mostly used for trigger setup and then exporting captured data as VCD files into GTKwave for viewing. SUMP1 also did not scale in width, depth or time, it was fixed at 16 events, 2 DWORDs and a 2^20 timestamp ( 1 Million Samples ) both in hardware and software. In 2016 BML decided to do a complete start-over on the SUMP RLE concept and developed SUMP2-RLE ( or just SUMP2 for short ). New Hardware, New Software. More features, better scaling – introducing SUMP2:

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The sump2.v verilog file is designed to work inside any FPGA or ASIC containing block RAM and scales in complexity from 1-4 bytes of events ( 8-32 triggerable and RLE compressible signals ) and 0-16 DWORDs of up to 512 non-compressed data bits. Depth and width of RAM scales on instantiation to best fit a wide range of FPGA technology. The full featured SUMP2 configuration is designed to be used on internal nodes within very large $100 – $1000 FPGAs. In this configuration for analyzing internal FPGA nodes it is very similar to proprietary FPGA vendor solutions such as Xilinx ChipScope and Altera SignalTap. SUMP2 has the advantage of being fully open and also offers RLE compression that can offer 10x – 1000x the time storage of similar FPGA logic analyzers not aided by hardware compression. Duty cycle hardware applications such a pulse-echo radar can readily achieve 5,000x compression using the new RLE engine with 2^32 timestamps. The scalability of SUMP2 also permits it to work in ultra low cost ( sub $5 ) FPGAs such as the Lattice iCE family. The Lattice iCEstick eval board at only $22 with included FTDI USB interface and PROM programming provides for a perfect SUMP2 platform for electronic debugging of Arduino and Raspberry Pi like projects involving 3V serial ports and GPIO. Communication between hardware and software over USB is all done using the Mesa Bus Protocol , an open serial protocol for transferring 32bit PCI reads and writes over UART, SPI and SERDES serial links between computers and FPGAs.

Lattice-iCEstick.png

Lattice-ICEstick-Layout-1.png

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To fit within the iCE40HX1K FPGA, sump2.v verilog RTL design is instantiated for 16 input events, no DWORDs and 1k depth of RLE capture RAM sampling at 96 MHz. The graphical backend software is sump2.py, a PyGame application used for arming the hardware and dumping and displaying the capture for analysis. Compared to the SUMP1 .NET app, the PyGame SUMP2 version is very fast. Although sump2.py supports exporting and importing VCD files, it is entirely not necessary to use a standalone VCD viewer such as GTKwave or Modelsim.

A simple example of a Unit Under Test.  Below pictured is a 10 MHz ( 100ns period ) oscillator driving a 74ACT161 4bit counter with a 74HC08 AND gate on the d(2) and d(3) upper bits of the counter. A push button switch to ground with a 10K pullup resets the counter. 8 nodes of interest are connected via Dupont ribbon cable to the iCEstick PMOD header.

IMG_1842.JPG

Short demonstration video of the sump2.py PyGame application:

The initial full capture of the reset button being released. The capture represents 4168 samples at 96 MHz using only 1K of RAM by utilizing RLE compression. RAM is hard partitioned 50/50 pre and post trigger.sump2_0003.png

SUMP2 has the ability of masking input events prior to arming which allows for greater RLE time compression. By double-clicking and “Hiding” the clk_10m signal prior to a new acquisition, the highly active clock signal is masked. This next capture without the 10 MHz clock is twice the length, or 83uS.  Also notice the very short reset switch bounce captured. Masking the LSB counter bits would further increase total capture time.

sump2_0004.png

Mouse scroll wheel can be used for zooming in and out in time, allowing for rapid detailed analysis and cursor measurements.

sump2_0000.png

Right-Clicking the mouse launches popup menus for tool selection.

sump2_popup_menu1.png

The left side popup allows for selecting a signal and then assigning it as a rising or falling edge trigger.

sump2_popup_menu2.png

Steps for building your own open-source SUMP2 Logic Analyzer for the Lattice iCEstick.

What is needed:

  1. $22 iCEstick from Mouser, Digikey or direct from Lattice. ( ICE40HX1K-STICK-EVN )
  2. Free FPGA Diamond Programmer software from Lattice.
  3. Windows Device Driver for the FT2232H USB chip from FTDI ( this may also be included with Lattice Programmer ).

and this free stuff from Black Mesa Labs:

  1. Bitfile for SUMP2 for the Lattice iCE40HX1K FPGA.
  2. bd_server.py – a Python TCP server for communicating to hardware over USB.
  3. sump2.py – a Python PyGame application. Handles triggers and waveform viewing.
  4. FPGA Design Files ( Optional, only needed if not using prebuilt Bitfile ).
  5. 5V Input shield PCB design in CopperConnection ( Optional ).

And finally, a bunch of text file documentation from Black Mesa Labs:

  1. Installation Instructions
  2. FAQ
  3. Program Launching instructions
  4. Troubleshooting guide
  5. Pinout for connecting flying leads to iCEstick
  6. Change Log for Software and Hardware
  7. Bug Report

EE Times Article by Clive “Max” Maxfield on SUMP2

Hackaday Article by Jenny List

Please enjoy SUMP2, a 96 MSPS 16bit 3V logic analyzer for only $22. Follow BML on Twitter for updates on SUMP2 and other open-source software and hardware projects from Black Mesa Labs.

EOF

Nice article ( in Russian ) and SUMP2

SUMP2 – 96 MSPS Logic Analyzer for $22

1″ 100W Hot-Plate for SMT Reflow

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[03.13.2016]

Black Mesa Labs has been using a $20 hot plate for a year now for soldering QFN ICs to PCBs using the BML Inverted Solder Ball reflow technique. This works great for soldering 0.5mm pitch QFN and LGA type packages that would otherwise require messy stencils and paste. Only issue so far has been the size ( 10″x10″x3″ ) and thermal mass of the commercial hot plate as it consumes precious microscope work area and unfortunately stays quite hot for 30+ minutes after a quick 4 minute single IC reflow job.  BML boards are mostly 1″x1″, so a 800W hot plate with a 6″ diameter heating surface is overkill for most jobs.

heating_element.jpg

Wanting something much smaller for a typical BML PCB – stumbled across this 24V DC heating element on Amazon for only $14. It is rated for 24V at 5-7 ohms ( or 4.8Amps ).  A surplus 19.5V DC 5A laptop power brick laying around BML seemed like a perfect match for this element.  BML has safety rules avoiding designs above 48V – so the 100Watt 20V DC supply coupled with the 24V element seemed like a great way to make a lot of heat in a small surface area in a short amount of time.

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First experiment was to see if this little element would reach +200C in under 4 minutes. Not wanting to cut up the laptop supply’s power connector – located this

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power connector adapter for only $5 and cut off the yellow Lenovo end of it and converted it to 0.100″ spaced Dupont connector instead. Hooked up a simple push button switch in line with the circuit – pressed the button and measured surface temperature with a digital thermometer – reached 200C in only 90 seconds!  Too fast for reflowing 40nm FPGAs unfortunately. Wanting to keep the 20V supply – needed to switch to pulse width modulation to slow down the thermal ramp to closely match solder reflow profile of 4 minutes to +200C. A relay? Nah – lets design a custom PCB with power FETs!

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After consulting with BML’s “all things analog expert on retainer” DP on how best to switch 100W at 20V – designed a small $2 2-layer PCB as a low-side switch using two IRLML6344TRPBFCT-ND 30V Power MOSFETs in parallel.  Design was drawn ( no schematic ) straight in CopperConnection Gerber drawing tool in less than 15 minutes and fabbed by OSH-Park in about 2 weeks for $2 for a ~1″ x 0.5″ 2-layer 0.8mm PCB.

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Rds On for this N-FET is 0.029 ohms at 5A ( or  725 mW ) which is near the 1.3W limit for the itty bitty SOT23 device. Not having any heatsinks other than the connection to the PCBs giant “Drain Plane” – opted to share the 5A load across two FETs in parallel. The N-Channel MOSFET’s Source is technically ground – but all the heat is dissipated through the Drain, so large pours on both PCB top and bottom were made to better dissipate the Rds On heat. Design is feed thru for + and – from the supply to the + and – for the load even though the + supply doesn’t touch the circuit at all.  Placed 3 different sized vias 0.125″, 0.079″ and 0.040″ so the board may be easily reused for other projects of various gauge wire needing high voltage and current switching.  A 100K resistor to GND ensures the FETs don’t turn on by themselves without a driver present (powerup Hi-Z) and a 1K series resistor to the Gate of both FETs limits the in-rush current. These Infineon  N-Channel FETs are only $0.29, come in a small SOT-23 package, can switch 5Amps from a 3V LVCMOS signal and are now BML’s go to device for power switching.

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Above is a Owon Scope capture of the FET turn on time ( Gate versus Drain ). CH2 ( Yellow ) is the Gate of the N-FET which is driven by LVCMOS 3.3V totem-pole from an AVR through a 1K series resistor. It takes 500ns for the Gate to go from 0V to 1V and then the FET turns on.  CH1 (Red ) is the Drain transitioning from pulled up ( via 1K thru the LED ) to clamping to GND. This transition takes about 2uS total.

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An Arduino Pro (above) was chosen as the PWM controller.  Most BML CPU designs are either RaspPi or Arduino-Zero based ( ARM 32bit ), but BML had this old Sparkfun board in a box and it was the right dimensions as a mechanical base for the project. The 1.5″ diameter heating element is suspended about 1″ in the air, so the wide 2″x2″ Pro board keeps everything from tipping over.
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Above picture shows everything cobbled together. A small piece of aluminum foil is wrapped around the element to keep flux from making a mess of it while under reflow. The heating element comes with 22 AWG solid wire crimped to it and extending about 2″ away. The wires are soldered to a 1×2 SIP connector which then mates to another 1×2 SIP connector on the FET board ( being able to remove the heating element from the circuit while under development was VERY important ).  The FET board is placed in the center of the Arduino Pro board atop some poster putty and held in place with the Enable wire (White ), the 1,500 resistor voltage drop network and a ground wire. The Pro can be powered from an FTDI USB cable of course, but to power it from the single Laptop supply, the voltage required dropping down from 20V to around 12V for the on board LDO.  Three 500 ohm leaded resistors each provide about a 2V drop while the AVR CPU is sipping 4mA, for a total drop of around 6V. A large 1K resistor provides 20mA to the red LED whenever the FET gates are turned on and the heating element is getting power.  Total cost was under $20 for the project – not counting the Arduino Pro in the junk box.MLX90614(E,K)SF-xxA.JPG

The Arduino was chosen over an FPGA as the PWM rate is really slow ( seconds ) and the Arduino makes it easy to expand the design and eventually interface to a Infrared Thermometer over I2C via existing tutorials and libraries.  Eventually the design could be expanded to measure the temperature at the surface of the FR4 under reflow for either reporting and / or control.  For now – the dead reckoning PWM method is plenty sufficient.  As the heating element contains very little thermal mass – it cools down in just seconds.

Above is the target solder reflow profile and below is the achieved profile as measured with a thermocouple on a scrap 1″x1″ FR4 PCB.

The GPL’d open source C++ source is available here hot_plate and is fairly straight forward.  When the button is pressed, the AVR starts a 4 minute PWM state machine that gradually increases the PWM duty cycle from 30% to 40% to 60% and then off.  Measuring a scrap piece of FR4 with a thermocouple mounted to it, an ideal reflow profile of 20-150C for 90 seconds, 150-200C for 90 seconds and finally 200-250C for 50 seconds was achieved. Pressing the button mid thermal cycle cancels the cycle. The AVR and giant Pro board is definitely overkill – but the PCB size made it a great platform to mount everything else to.

A word on safety – although this project is under 48V – the amount of heat it can generate could definitely start a fire if powered up in the wrong place ( under a stack of old newspapers for example ) .  To prevent any potential small fires from starting 3 levels of safety were built it. 1) the Arduino runs the heat profile only when the pushbutton is pressed and then automatically turns itself off after the profile time is complete. 2) The 20V 5A power to the electronics goes through a toggle switch. 3) The original laptop barrel connector is quickly and visibly disconnected from the setup when reflow is complete allowing the hotplate to be visibly disconnected from the power supply when not used.

Below is a YouTube video of a Lattice ICE5LP4K-SGN48 FPGA reflowing on the “Mesa Logic DIP” PCB using the BML Inverted Solder Ball reflow technique. This is a general purpose FPGA board on a 0.100″ grid providing 24 user IOs in a 0.600″ x 1.6″ package. This board has a destiny to reach 100,000 feet (~30km) this coming May as a HAB controller for a weather balloon. It will communicate with both an “on balloon” Raspberry Pi and with a ground station via a RockBLOCK Iridium satellite modem using Mesa Bus Protocol. Stay tuned to Black Mesa Labs for an upcoming blog on all the details of the custom HAB electronics.

 

 

1″ 100W Hot-Plate for SMT Reflow

Mesa Bus Protocol

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Enclosed text file ( mesa_bus  ) is the open-source  Mesa Bus Protocol for transferring bytes between CPUs and FPGAs. It is intended to transfer data between 50 Kbps up to 10 Gbps over UART to SERDES links with just a few wires and very little hardware overhead. It is a very small gate foot print byte transport protocol for encapsulating and transferring payloads of higher protocols (0-255 bytes per payload). Think of it like a cross between Ethernet and USB 3.1. The advantages Mesa Bus Protocol has over USB, Ethernet and PCI is that it fits easily within a $3 FPGA and may be bus mastered either by a PC with a FTDI cable or any old ARM/AVR Arduino CPU (or RPi) with just two standard UART serial port pins. As it is ASCII based, Mesa Bus Protocol is also very portable to wireless devices such as Bluetooth SPP and the RockBLOCK satellite modem for the Iridium network .

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Have you ever placed a regular envelope inside an interoffice envelope? Mesa Bus is that interoffice envelope. Where Ethernet transfers UDP, TCP, HTTP,etc packets without higher level knowledge – Mesa Bus can transfer SPI, I2C, Digital Video, 32bit LocalBus,etc  from chip to chip without protocol knowledge.  Mesa Bus works with up to 254 devices with only 2 wires between each device. Black Mesa Labs currently uses Mesa-Bus with the Mesa-Logic MCM FPGA and BD_SHELL.exe windows executable, Python, or an Arduino-Zero ( ARM ) as bus master. Payloads have been digital video ( 800×600 at reduced frame rates over a 40 MHz synchronous Mesa Bus link ) and 32bit local bus write and read cycles (PCI-ish) to FPGA registers and also for FPGA flash firmware updates. Mesa Bus Protocol fully supports prototyping embedded software 1st on a PC in a rapid scripting language like Python as it is clear ASCII that may be transported over a standard FTDI cable or Bluetooth SPP connection.

 

 

 

 

Mesa Bus Protocol

The Future is Now!

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09.16.2015 – Black Mesa Labs was delivered a very unexpected large 2’x2′ (60×60 cm) package today. BML generally uses a U.S. quarter as a scale reference – but for this – a Pint glass is in order:

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Examining the shipping label – Realized the new Lattice ICE-Ultra FPGAs had arrived 3 weeks early. This new 40nm FPGA from Lattice is a game changer for both BML and the Maker Movement.

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Backstory – Back in May 2015, BML started experimenting with Lattice ICE40 family  as an alternative to large Xilinx TQFP devices for BML designs.  The ICE40LP384-SG32 appeared to be a game changer for BML as it was both low cost ( sub $2 ) and in a 2-layer PCB friendly package ( SG32 ). The big two FPGA vendors ( let’s call them Brand-X and Brand-A ) have gone entirely BGA for their FPGAs – which is completely useless for BML and the OSH-Park style 2-layer Maker Movement PCB designs and assembly. Lattice ( although offering mostly BGA ) has FPGAs in QFN packages ( aka MLFs, SGs ) which can be hand soldered. Sadly – the LP384 proved limited in capabilities – a simple Mesa-Bus bridge design that would easily fit in 200 Xilinx LCELLs completely filled the LP384 as 1/2 the LUTs were used as route-throughs ( consuming limited gates for simple routing ). The LP384 turned out to be about as useful as a large CoolRunner CPLD. But wait….

In June 2015 – Lattice announced that their newer ICE-Ultra ICE5LP4K ( 4,000 Logic Cells ) that was originally BGA only would soon be available in a SG48 package (QFN).  4,000 FPGA Logic Cells for $5 in a 7x7mm package that is 2-layer PCB friendly –  Sign me up!  Fast forward to July – the ICE5LP4K-SG48s were nowhere to be found in normal distribution.  BML contacted both Digikey and Lattice and learned the devices would need to be special ordered in quantity in uncut reels – with a minimum reel count of 50, and a minimum order of 10 reels. The ICE5LP4K FPGAs themselves are only $5, but 10x50x$5= $2,500 – not exactly within BML $100/month beer money budget.  Through persistence and careful negotiations, BML was able to secure a “Special Order” for a single reel of Qty-50 FPGAs – or $250 – manageable. Placed the order in July with an ETA of October 7, 2015 – but they arrived 3 weeks early – Christmas in September!

Inside the giant box was a little LP vinyl sized box and a whole lot of bubble wrap:

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Inside the little box, the giant reel:

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Unfurling the reel – the actual chips – this is all fifty chips:

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Single chip- 4,000 Logic Cells in 7x7mm package for $5 – how cool is that?

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Backside you can see how it is 2-layer friendly unlike BGA devices:

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This FPGA is really a game changer as it is a true FPGA, much more than just a simple CPLD.  It contains 80 Kbits of SRAM, an on chip ~48MHz oscillator, 39 LVCMOS IOs and 3520 Logic Elements ( LUTS + FlipFlop ). A close Xilinx equivalent ( in a much larger 14x14mm TQFP  package ) would be a device like the Spartan3 XC3S200. This new Lattice device is 1/4 the size and 1/3 the price and 2-layer PCB compatible. 4K LEs aren’t enough for a custom CPU or DSP work – but ample logic for bus bridging, UART designs and complicated FSMs ( Finite State Machines ).  My general rule is 100 LEs a designer can easily consume in a short day of RTL design, 1,000 LEs in a week, 10,000 LEs in a month. 4K LEs is a perfect canvas size for BML designs.

Next up is assembly. BML has 3 PCBs that were waiting for these devices to arrive, Mesa-Video, Mesa-Logic and Mesa-GPIO:

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Initial use for this chip is the Mesa-Bus bridge function – a daisy-chained serial bus that self enumerates based on location in a serial chain and converts clear text ASCII UART serial into either SPI or I2C. Purpose of Mesa-Bus is to provide USB like expansion to simple microcontrollers like Arduinos using only 2 pins ( TXD and RXD UART Serial ). Stay Tuned – the family of Mesa-Modules are about to come alive!

The Future is Now!