SUMP2 – 96 MSPS Logic Analyzer for $22

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2016.22.22 : SUMP2 now also available for RaspPi+icoBoard here.

2016.12.13 : Great video on SUMP2 from Bil Herd at Hackaday.

2016.10.31: Thanx to SteveDC, a 3D printed case is now available for SUMP2 here.

2016.10.30 : SUMP2 5V Input shield is now available from OSH-Park for $5. BML can also design similar shields for RS232,RS422/485,LVDS and CAN Bus if there is any interest.

2016.10.24 : Black Mesa Labs has an ongoing mission to develop easy to use and fully capable open-source hardware and software tools that make engineering electronics easier. One such tool is this new low cost open-source logic analyzer called SUMP2 for people who otherwise work in the blind without an oscilloscope or logic analyzer on their bench top.  BML’s 1st incarnation called SUMP1-RLE in 2014 was a 16bit FPGA based logic analyzer that performed real-time hardware compression and decompression. The decompressed data was streamed out over USB using the open SUMP protocol ( hence the name ), allowing it to be used with the excellent Java software from the original 2007 sump.org project. The SUMP1-RLE project was later enhanced from just 16 triggerable events to also include 2 DWORDs of “data” ( additional 64bits of non-triggering non-compressed signals ) and advanced triggering options. Including the data DWORDs made SUMP1 a useful tool for complex FPGA development debugging of internal FPGA event nodes and data paths. These new features required new custom software, written by BML in .NET for Windows. The software was functional, but graphically slow and was mostly used for trigger setup and then exporting captured data as VCD files into GTKwave for viewing. SUMP1 also did not scale in width, depth or time, it was fixed at 16 events, 2 DWORDs and a 2^20 timestamp ( 1 Million Samples ) both in hardware and software. In 2016 BML decided to do a complete start-over on the SUMP RLE concept and developed SUMP2-RLE ( or just SUMP2 for short ). New Hardware, New Software. More features, better scaling – introducing SUMP2:

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The sump2.v verilog file is designed to work inside any FPGA or ASIC containing block RAM and scales in complexity from 1-4 bytes of events ( 8-32 triggerable and RLE compressible signals ) and 0-16 DWORDs of up to 512 non-compressed data bits. Depth and width of RAM scales on instantiation to best fit a wide range of FPGA technology. The full featured SUMP2 configuration is designed to be used on internal nodes within very large $100 – $1000 FPGAs. In this configuration for analyzing internal FPGA nodes it is very similar to proprietary FPGA vendor solutions such as Xilinx ChipScope and Altera SignalTap. SUMP2 has the advantage of being fully open and also offers RLE compression that can offer 10x – 1000x the time storage of similar FPGA logic analyzers not aided by hardware compression. Duty cycle hardware applications such a pulse-echo radar can readily achieve 5,000x compression using the new RLE engine with 2^32 timestamps. The scalability of SUMP2 also permits it to work in ultra low cost ( sub $5 ) FPGAs such as the Lattice iCE family. The Lattice iCEstick eval board at only $22 with included FTDI USB interface and PROM programming provides for a perfect SUMP2 platform for electronic debugging of Arduino and Raspberry Pi like projects involving 3V serial ports and GPIO. Communication between hardware and software over USB is all done using the Mesa Bus Protocol , an open serial protocol for transferring 32bit PCI reads and writes over UART, SPI and SERDES serial links between computers and FPGAs.

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To fit within the iCE40HX1K FPGA, sump2.v verilog RTL design is instantiated for 16 input events, no DWORDs and 1k depth of RLE capture RAM sampling at 96 MHz. The graphical backend software is sump2.py, a PyGame application used for arming the hardware and dumping and displaying the capture for analysis. Compared to the SUMP1 .NET app, the PyGame SUMP2 version is very fast. Although sump2.py supports exporting and importing VCD files, it is entirely not necessary to use a standalone VCD viewer such as GTKwave or Modelsim.

A simple example of a Unit Under Test.  Below pictured is a 10 MHz ( 100ns period ) oscillator driving a 74ACT161 4bit counter with a 74HC08 AND gate on the d(2) and d(3) upper bits of the counter. A push button switch to ground with a 10K pullup resets the counter. 8 nodes of interest are connected via Dupont ribbon cable to the iCEstick PMOD header.

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Short demonstration video of the sump2.py PyGame application:

The initial full capture of the reset button being released. The capture represents 4168 samples at 96 MHz using only 1K of RAM by utilizing RLE compression. RAM is hard partitioned 50/50 pre and post trigger.sump2_0003.png

SUMP2 has the ability of masking input events prior to arming which allows for greater RLE time compression. By double-clicking and “Hiding” the clk_10m signal prior to a new acquisition, the highly active clock signal is masked. This next capture without the 10 MHz clock is twice the length, or 83uS.  Also notice the very short reset switch bounce captured. Masking the LSB counter bits would further increase total capture time.

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Mouse scroll wheel can be used for zooming in and out in time, allowing for rapid detailed analysis and cursor measurements.

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Right-Clicking the mouse launches popup menus for tool selection.

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The left side popup allows for selecting a signal and then assigning it as a rising or falling edge trigger.

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Steps for building your own open-source SUMP2 Logic Analyzer for the Lattice iCEstick.

What is needed:

  1. $22 iCEstick from Mouser, Digikey or direct from Lattice. ( ICE40HX1K-STICK-EVN )
  2. Free FPGA Diamond Programmer software from Lattice.
  3. Windows Device Driver for the FT2232H USB chip from FTDI ( this may also be included with Lattice Programmer ).

and this free stuff from Black Mesa Labs:

  1. Bitfile for SUMP2 for the Lattice iCE40HX1K FPGA.
  2. bd_server.py – a Python TCP server for communicating to hardware over USB.
  3. sump2.py – a Python PyGame application. Handles triggers and waveform viewing.
  4. FPGA Design Files ( Optional, only needed if not using prebuilt Bitfile ).
  5. 5V Input shield PCB design in CopperConnection ( Optional ).

And finally, a bunch of text file documentation from Black Mesa Labs:

  1. Installation Instructions
  2. FAQ
  3. Program Launching instructions
  4. Troubleshooting guide
  5. Pinout for connecting flying leads to iCEstick
  6. Change Log for Software and Hardware
  7. Bug Report

EE Times Article by Clive “Max” Maxfield on SUMP2

Hackaday Article by Jenny List

Please enjoy SUMP2, a 96 MSPS 16bit 3V logic analyzer for only $22. Follow BML on Twitter for updates on SUMP2 and other open-source software and hardware projects from Black Mesa Labs.

EOF

SUMP2 – 96 MSPS Logic Analyzer for $22

1″ 100W Hot-Plate for SMT Reflow

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[03.13.2016]

Black Mesa Labs has been using a $20 hot plate for a year now for soldering QFN ICs to PCBs using the BML Inverted Solder Ball reflow technique. This works great for soldering 0.5mm pitch QFN and LGA type packages that would otherwise require messy stencils and paste. Only issue so far has been the size ( 10″x10″x3″ ) and thermal mass of the commercial hot plate as it consumes precious microscope work area and unfortunately stays quite hot for 30+ minutes after a quick 4 minute single IC reflow job.  BML boards are mostly 1″x1″, so a 800W hot plate with a 6″ diameter heating surface is overkill for most jobs.

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Wanting something much smaller for a typical BML PCB – stumbled across this 24V DC heating element on Amazon for only $14. It is rated for 24V at 5-7 ohms ( or 4.8Amps ).  A surplus 19.5V DC 5A laptop power brick laying around BML seemed like a perfect match for this element.  BML has safety rules avoiding designs above 48V – so the 100Watt 20V DC supply coupled with the 24V element seemed like a great way to make a lot of heat in a small surface area in a short amount of time.

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First experiment was to see if this little element would reach +200C in under 4 minutes. Not wanting to cut up the laptop supply’s power connector – located this

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power connector adapter for only $5 and cut off the yellow Lenovo end of it and converted it to 0.100″ spaced Dupont connector instead. Hooked up a simple push button switch in line with the circuit – pressed the button and measured surface temperature with a digital thermometer – reached 200C in only 90 seconds!  Too fast for reflowing 40nm FPGAs unfortunately. Wanting to keep the 20V supply – needed to switch to pulse width modulation to slow down the thermal ramp to closely match solder reflow profile of 4 minutes to +200C. A relay? Nah – lets design a custom PCB with power FETs!

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After consulting with BML’s “all things analog expert on retainer” DP on how best to switch 100W at 20V – designed a small $2 2-layer PCB as a low-side switch using two IRLML6344TRPBFCT-ND 30V Power MOSFETs in parallel.  Design was drawn ( no schematic ) straight in CopperConnection Gerber drawing tool in less than 15 minutes and fabbed by OSH-Park in about 2 weeks for $2 for a ~1″ x 0.5″ 2-layer 0.8mm PCB.

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Rds On for this N-FET is 0.029 ohms at 5A ( or  725 mW ) which is near the 1.3W limit for the itty bitty SOT23 device. Not having any heatsinks other than the connection to the PCBs giant “Drain Plane” – opted to share the 5A load across two FETs in parallel. The N-Channel MOSFET’s Source is technically ground – but all the heat is dissipated through the Drain, so large pours on both PCB top and bottom were made to better dissipate the Rds On heat. Design is feed thru for + and – from the supply to the + and – for the load even though the + supply doesn’t touch the circuit at all.  Placed 3 different sized vias 0.125″, 0.079″ and 0.040″ so the board may be easily reused for other projects of various gauge wire needing high voltage and current switching.  A 100K resistor to GND ensures the FETs don’t turn on by themselves without a driver present (powerup Hi-Z) and a 1K series resistor to the Gate of both FETs limits the in-rush current. These Infineon  N-Channel FETs are only $0.29, come in a small SOT-23 package, can switch 5Amps from a 3V LVCMOS signal and are now BML’s go to device for power switching.

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Above is a Owon Scope capture of the FET turn on time ( Gate versus Drain ). CH2 ( Yellow ) is the Gate of the N-FET which is driven by LVCMOS 3.3V totem-pole from an AVR through a 1K series resistor. It takes 500ns for the Gate to go from 0V to 1V and then the FET turns on.  CH1 (Red ) is the Drain transitioning from pulled up ( via 1K thru the LED ) to clamping to GND. This transition takes about 2uS total.

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An Arduino Pro (above) was chosen as the PWM controller.  Most BML CPU designs are either RaspPi or Arduino-Zero based ( ARM 32bit ), but BML had this old Sparkfun board in a box and it was the right dimensions as a mechanical base for the project. The 1.5″ diameter heating element is suspended about 1″ in the air, so the wide 2″x2″ Pro board keeps everything from tipping over.
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Above picture shows everything cobbled together. A small piece of aluminum foil is wrapped around the element to keep flux from making a mess of it while under reflow. The heating element comes with 22 AWG solid wire crimped to it and extending about 2″ away. The wires are soldered to a 1×2 SIP connector which then mates to another 1×2 SIP connector on the FET board ( being able to remove the heating element from the circuit while under development was VERY important ).  The FET board is placed in the center of the Arduino Pro board atop some poster putty and held in place with the Enable wire (White ), the 1,500 resistor voltage drop network and a ground wire. The Pro can be powered from an FTDI USB cable of course, but to power it from the single Laptop supply, the voltage required dropping down from 20V to around 12V for the on board LDO.  Three 500 ohm leaded resistors each provide about a 2V drop while the AVR CPU is sipping 4mA, for a total drop of around 6V. A large 1K resistor provides 20mA to the red LED whenever the FET gates are turned on and the heating element is getting power.  Total cost was under $20 for the project – not counting the Arduino Pro in the junk box.MLX90614(E,K)SF-xxA.JPG

The Arduino was chosen over an FPGA as the PWM rate is really slow ( seconds ) and the Arduino makes it easy to expand the design and eventually interface to a Infrared Thermometer over I2C via existing tutorials and libraries.  Eventually the design could be expanded to measure the temperature at the surface of the FR4 under reflow for either reporting and / or control.  For now – the dead reckoning PWM method is plenty sufficient.  As the heating element contains very little thermal mass – it cools down in just seconds.

Above is the target solder reflow profile and below is the achieved profile as measured with a thermocouple on a scrap 1″x1″ FR4 PCB.

The GPL’d open source C++ source is available here hot_plate and is fairly straight forward.  When the button is pressed, the AVR starts a 4 minute PWM state machine that gradually increases the PWM duty cycle from 30% to 40% to 60% and then off.  Measuring a scrap piece of FR4 with a thermocouple mounted to it, an ideal reflow profile of 20-150C for 90 seconds, 150-200C for 90 seconds and finally 200-250C for 50 seconds was achieved. Pressing the button mid thermal cycle cancels the cycle. The AVR and giant Pro board is definitely overkill – but the PCB size made it a great platform to mount everything else to.

A word on safety – although this project is under 48V – the amount of heat it can generate could definitely start a fire if powered up in the wrong place ( under a stack of old newspapers for example ) .  To prevent any potential small fires from starting 3 levels of safety were built it. 1) the Arduino runs the heat profile only when the pushbutton is pressed and then automatically turns itself off after the profile time is complete. 2) The 20V 5A power to the electronics goes through a toggle switch. 3) The original laptop barrel connector is quickly and visibly disconnected from the setup when reflow is complete allowing the hotplate to be visibly disconnected from the power supply when not used.

Below is a YouTube video of a Lattice ICE5LP4K-SGN48 FPGA reflowing on the “Mesa Logic DIP” PCB using the BML Inverted Solder Ball reflow technique. This is a general purpose FPGA board on a 0.100″ grid providing 24 user IOs in a 0.600″ x 1.6″ package. This board has a destiny to reach 100,000 feet (~30km) this coming May as a HAB controller for a weather balloon. It will communicate with both an “on balloon” Raspberry Pi and with a ground station via a RockBLOCK Iridium satellite modem using Mesa Bus Protocol. Stay tuned to Black Mesa Labs for an upcoming blog on all the details of the custom HAB electronics.

 

 

1″ 100W Hot-Plate for SMT Reflow

Backdoor to Scope Out

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Sometimes the simplest projects are the best. This is my “Backdoor to Scope Out” project.  I use my “Backdoor” connection to interface a computer to FPGAs when a regular bus ( PCI ) isn’t available.  What I call the “Backdoor” is just a FTDI 1×6 asynch serial connection at 921,600 baud – pretty much standard in Arduino land – I just use it as a really slow bus bridge into FPGAs.  As soon as a regular connection ( PCI for example ) is working, the backdoor connection goes unused.  This project repurposes the otherwise dormant Backdoor header for debug to drive state signals out to an oscilloscope using low cost cables. The cable solution I chose was 1/8″ TRRS ( headphone jack ) to RCA Audio-Left,Audio-Right, Composite-Video that was standardized by the Camcorder industry.  The cables are cheap ( $10 ) and fairly high quality that go 3′ to 6′ from a compact 1/8″ headphone plug to 3 RCAs that are easily converted to BNC.

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The first board converts a 0.100″ Header to a thru-hole TRRS jack. I was shocked and disgusted to discover that “shield” isn’t used for signal return ( Ground ) on the TRRS connector – but instead used for Audio.

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The second board converts the 1×6 FTDI header to the “new” 1×6 reversible scope-out header.  I wanted to make the connection reversible so that the ~bulky~ 1/8″ plug and socket could go in 1of4 orientations when plugged in to guarantee clearance from other components that may be on a PCB.

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The final test for the project was to drive a 50 MHz and 40 MHz square wave onto 2 of the 3 RCA cables over 6 feet and observe final signal integrity and any potential cross talk. End result was great – perfect for FPGA state debugging. Total cost for complete 3 channel solution was under $20. Now I have a robust 3 channel 0.100″ connection to an oscilloscope using readily available cables.

Backdoor to Scope Out

Saleae Logic

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One of my favorite tools ( that I forgot to mention when talking bout my Microscope and Oscilloscope ) is my 8bit Saleae Logic Analyzer. It is a $150 8bit LVCMOS, 24 MSPS logic analyzer that works by sampling signals using a Cypress CY7C68013A, a single chip that contains a synchronous input FIFO, 8051 uC and a USB 2.0 interface.  The hardware is not all that impressive, but the software is mind blowing fantastic. It is a full waveform GUI that is easy to configure and has built in decoding for UART, SPI, I2C, etc. The most impressive feature is that the samples aren’t stored locally, but in Windows RAM and the UI makes it trivial to acquire over a billion samples over a 10 second period and rapidly navigate those billion samples visually for things like spurious interrupts, etc. It is really a great tool for capturing a tremendous amount of data and sorting through it.

Sadly, Saleae has stopped making the original low cost 8bit logic. As far as I can piece together, they had them manufactured overseas and clones of the $150 Saleae started showing up on eBay for $15. One company even brazenly uses a picture from the Saleae website showing that the Saleae software will run on their PCB. It turns out that the Saleae crown jewel ( the software ) is available for downloading and the hardware they charge $150 for has a $10 BOM and is trivial to copy.  Hard lesson to learn. IBM learned it the hard way and made Microsoft very rich. Now Saleae is planning to manufacture their new products themselves – which I can’t fathom their volume being high enough to justify.  Its too bad they don’t open-source their old hardware design and sell their software ( with keys ) for the clone market. As of today,you can’t buy their old products anymore and their new products have a long lead time for delivery. The Amazon and Sparkfun distribution channels are completely dry of anything from Saleae. I fear for their long term survival.

Anyways – great products, great software technology – highly recommended.

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TRRS 3.5mm Plugs and Jacks

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[01.14.2015]  I designed a very simple $2 circuit board to breakout a “TRRS” (Tip-Ring-Ring-Shield ) 3.5mm headphone jack that you see all over the place these days. I’m wanting to drive multiple channels of an oscilloscope and the 3 RCA to 3.5mm TRRS cables seem to be in use everywhere and would be useful for low bandwidth ( ~50MHz ) applications for capturing digital state transitions ( not so much signal integrity ). The TRRS jacks exist in smart phones to support earbud head sets with microphones and also in video devices ( video iPod, camcorder, etc ) to deliver Left and Right audio plus a Composite video on 3 conductors plus a return instead of the normal “TRS”  Tip-Rings-Shield 2 conductor stereo connector.  Digging into to their pinout I was astonished to find out that mechanically all the TRRS plugs and receptacles seem compatible, but electrically EVERYBODY wires them up differently. The return signal actually isn’t the “S” ( shield ) for most manufacturers ( although it is for some ).  The “S” is return for 3.5mm mono, 3.5mm stereo, but not necessarily 3.5mm TRRS 3 conductor. Some devices go in the TRRS order of “Audio-Audio-Ground-Video”, some “Audio-Video-Ground-Audio”, some “Audio-Audio-Video-Ground”.  I looked up various TRRS to RCA cables on Amazon and about 1/2 the reviews said things like “piece of junk – didn’t work” or “audio on only one channel, no video” or “didn’t work until I plugged the red into video and yellow into audio jack”.  What a disaster.  How much does this cost Amazon in returns? Bad design decisions like these are made by electrical engineers and it really makes the industry look bad. I ended up going with the “Camcorder” ~standard~ as at least multiple manufactures agreed to it for video cameras ( but of course I won’t be able to use an Apple video cable ).  I found a good writeup up on this whole TRRS mess here . To think electrical engineers helped get men on the moon in 1969.

TRRS 3.5mm Plugs and Jacks

USB 2.0 FTDI 12Mbps Serial Converter Board Assembly

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[ 01.12.2015 ] Assembled my new USB 2.0 12Mbps UART board today.  Thought I would take the opportunity to blog about the entire process from start to finish – board design, procurement, surface mount assembly and final test.

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[ 12.23.2014 ] Started new ExpressPCB 2-layer design for a small 1″x0.5″ board to replace a standard 1Mbps FTDI Cable but run 12x faster using a USB 2.0 chip from FTDI – the FT232H.  All of my previous FTDI board designs have used the FT232R as it is a smaller chip that includes an oscillator and all the USB passives on chip.  The FT232R interfaces to USB at a conservative 12 Mbps versus SERDES 480 Mbps for the FT232H.  The FT232H requires a lot more support circuitry ( 12 MHz precision oscillator, protection diodes and is in a bigger package ).  Expecting a 2-layer PCB to work at 480 Mbps was a huge $3 gamble I was willing to take.

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[ 12.26.2014 ] Finished the design ( working on it part time – had other things going on the last few days ). Typical design flow is schematic design and then have a computer autoroute. My flow is quite different in that I manually place components where I think they can be routed using only two layers and also assembled by hand in as small area as possible. Using ExpressPCB version 7.0.2 (only), layout is done manually using a vector drawing program.  Red signifies copper on the top, green copper on the bottom, yellow silkscreen on top for labeling. Designing a PCB like this is very much a challenging puzzle.  After I finish the design, I import the ExpressPCB file into CopperConnection and export a single *.ZIP containing layer Gerbers and Excellon drill files in OSH-Park selected format. This process takes about 10 seconds. I could actually layout my board design in CopperConnection – but I already know ExpressPCB  – so why bother learning a new tool? ExpressPCB is a great service for at work when I need a board fast. When I’m not in much of a hurry, OSH-Park is super inexpensive and high quality.

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[ 12.26.2014 ] Uploaded Gerber and Excellon *.ZIP file of design to OSH-Park. The website takes a few minutes and presents a rendering of all the different layers ( Copper, Solder Mask, Silkscreen, Drill holes ). Approve and purchase the design 0.61×1.21 inch (15.39×30.66 mm) 2 layer board for $3.65

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Here is an example OSH-Park panel that I found on the web that they showed at a Makerfaire in Portland in 2013. Notice how small all the designs are and how much daylight shines through. Their software does a fantastic job of panelizing multiple small gerber designs. Other low cost PCB places like IteadStudio stick with simple fixed rectangles on a 5x5cm grid and charge on those dimensions even if your design is much smaller. I often look at other people’s OSH-Park designs at flickr site to see how far they stretch the 2 layer and 4 layer capabilities.

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[ 01.10.2015 ]  Bare boards arrive in the mail. They usually have rough snap-off edges which are easily filed down with a metal file.

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[ 01.12.2015 ] Surface Mount Assembly begins.  My tools are a 10x/30x microscope, a Weller-Ungar 921ZX soldering station with a screwdriver tip, GC Electronics Liquid solder-flux 10-4202, Kester “44 Rosin Core” lead solder 66/44 0.5mm .020″, Chem-Wik 0.075″ solder wick,  Isopropyl Alcohol 99.8% IPA, Cotton Swabs, Dental Pick, Tweezer and “Dexter” leather gloves. I also have a 4″ surplus case fan at the back of my microscope to take away the fumes.

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I always start by placing the QFP 1st as alignment is crucial with 0.5mm pitch between pins. Once the package is perfectly aligned ( 10x magnification ) I pour solder flux liberally along the perimeter. Flux is amazing stuff, not only does it perform Jedi mind control on molten lead to seek out copper and avoid solder mask – but it is wonderfully sticky stuff and does a fairly decent job of keeping the QFP from drifting out of alignment.  That said – I always tack down the corners first with just a bit of solder and then pour the solder on thick – rolling across all the leads. End result – complete ugly mess, shorts everywhere – but the leads are all attached to their pads in perfect alignment.

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Pass-2 ( you knew there had to be a pass-2, right ? ) – Solder Cleanup.  The wick combined with the flux on the board magically sucks up the excess solder shorting all the leads.  This step gets really hot really fast. I protect myself ( finger tips ) with my Dexter gloves ( thin unlined leather ) so I can position the wick and not burn myself.  I protect the chip by only wicking about 4 pins at a time then pull back and let the IC cool down for a few seconds before proceeding.  Takes patience but perfectly soldering an internally fried chip to a board is a real bummer. I do own a nice hot air reflow station where I can remove bad ICs -but I generally would rather just start a new board assembly from scratch than rework a bad one.

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Pass-3 : This pass is optional, but is worth the effort.  Apply lots of IPA ( the kind that makes you go blind – not the tasty beer ) and cotton swab scrubbing to remove all the flux.

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Pass-4 : With the QFP clean, I crank my microscope up from 10x to 30x and go around to each pin with a dental pick and check for bad solder joints ( loose pins ) or any shorts. I usually don’t find any, but the time to check is before all the other components are soldered to the board as access to the QFP pins becomes difficult if there are other components around.

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Once the QFP is on everything else is pretty straight forward.  I only use 0603 for Bypass caps ( 0.1uF ) and 0805 10uF Bulk Caps and 0805 resistors.  This speeds up assembly as I don’t need to look up each component in the design file, I can tell just by the pad size and what its connected to determine what to place.  For example – I never connect a 0805 resistor between power and ground – so it must be a 10uF bulk cap.  For the small SMT 0603s and 0805s I drop a bit of solder on 1 of 2 pads, then apply to component with tweezer and resolder the 1st pad to the component, then with the component firmly ( fully planar ) attached to the board, I apply solder and the iron tip to the 2nd pad. After this, the 1st pad usually needs some more solder to make a good looking connection.  Thats it – I’m done with assembly!

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Before test – I take a moment to reflect and decide what I would do differently to make assembly easier in the future.  For this design the microUSB connector was a problem. It is designed for solder paste and oven reflow assembly as the leads are recessed behind the shield housing.  I was able to solder them eventually, but a little more space between the connector and QFP would have been better. Mini-USB is MUCH easier to hand solder. Another issue I discovered is the shield extending behind the leads unexpectedly results in the shield resting above my 5V trace on the top side.  The solder mask is the only insulation preventing a short from 5V to shield return.  Prior to plugging into my computer, I applied my 5V DC supply to 5V PCB rail and the shield and confirmed no short.  This is OK for a one-off, but I immediately created a new “fixed” version of this design and moved the 5V trace south about 0.010″ to clear the shield. For $3.50 I will probably fab out this “fixed” version and scrap the remaining 2 unstuffed PCBs of Gen-1 if  I decide I need more than 1 unit.  The micro USB connector was the only issue, so moving on….

Time for test. Plug and pray a micro USB cable from my computer into the board.  And look at that! COM5 ready for use.

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1st test is to send 9,600 baud to my scope. Bit length is about 100us, or roughly 10,000 Baud.

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2nd test to send 921,600 baud to my scope. Now the bit length is about 1us, or roughly 1Mbaud.

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3rd and final test, run my Powershell  script that talks directly to FTDI device driver DLL and configure port for 12Mbaud.

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Excellent! I’m in business.  I now have a USB 2.0 to 12Mbps UART serial interface into my FPGA designs that is electrically and mechanically compatible with my existing FPGA boards ( that are designed for the industry standard FTDI cable ).  That ends my Black Mesa activity for tonight.  Next tasks are to change my FPGA design for the faster baud rate ( simple divisor setting in Verilog ) and establish Backdoor communications (Register Reads and Writes using BD_SHELL.exe ) and then time SUMP.exe data dumps from FPGA to computer and compare date rates between 1Mbps cable and 12Mbps board. Due to Windows and Powershell limitations – it may or may not be faster.  If it is faster ( like 10x faster ) – my next iteration of the design is ready to be assembled. This uses the same chip, but interfaces using 16 wires over a Nano x16 header instead of the FTDI 2 wire 1×6 connector. Spec says transfer rates should be 40 MBytes/Sec ( 320 Mbps ) – which theoretically would be 27x faster than my existing design that is already 12x faster than my existing FTDI cable. That project is for another day however.

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USB 2.0 FTDI 12Mbps Serial Converter Board Assembly

The Black Mesa Lab scopes – making it all possible

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My 10x / 30x microscope and my 2 GigaSample/Second oscilloscope are my two most cherished tools. Without my microscope, there is no way I could possibly hand solder 0603 caps and 0.5mm pitch TQFP ICs.  Without my oscilloscope, I would be completely blind to electronic signals transitioning a billion times a second. This link isn’t my exact scope, but it has similar attributes. I REALLY wish I had bought the more expensive 4 Channel Owon scope – but oh well – make due. My largest FPGA PCB is 2″x2″ so a small scope like this is perfect for SMT assembly. Boards larger than 6″x6″ would require a scope with a boom extending arm like this.

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My friend DaveP built a custom iPhone4S to microscope adapter so I could take incredibly clear digital pictures using my iPhone’s 8MP camera. The adapter is a $1 piece of PVC pipe with a carefully measured slit the iPhone slides into at the exact right distance from the eyepiece.

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For $10 I purchased a micrometer slide that allows me to measure down to 0.01mm.

I dropped and broke the Keyfob to my car the other day, using my microscope I was able to solder the small SMT switch that was shocked loose from the impact.

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The Black Mesa Lab scopes – making it all possible