IceZero FPGA Board for RaspPi


2017.02.07 : BML has been very much enchanted with the Lattice FPGA boards for Raspberry Pi, IcoBoard , BlackIce and IceHat. The IceZero board is a BML creation that attempts to combine the best features of all 3 boards into a single design. Hackaday article here.

[ IceZero Block Diagram ]


[ IceZero features common with other designs ]

  1. Fully Open-Source Hardware and Software Design.
  2. Lattice ICE40HX4K FPGA that supports Clifford Wolf’s Project IceStorm tool chain.
  3. Interfaces to Raspberry Pi 2×20 GPIO Header for both power and bus interfaces.
  4. PROM programmable directly from Rasp Pi, no JTAG programmer required.
  5. External SRAM, supporting soft CPU core designs ( code execution ).
  6. Extra large SPI PROM, supporting soft CPU core designs ( code storage ).
  7. Industry standard PMOD expansion headers

[ IceZero features that are BML specific ]

  1. Mesa Bus Protocol 32 MHz SPI link between CPU and FPGA.
  2. 2-Layer PCB design. Orderable via OSH-Park or Gerbers for Downloading.
  3. FTDI 1×6 USB Serial Cable header for use with PC instead of Pi ( or as a soft CPU debug Trace Port ).
  4. Single Pi UART plumbed to FPGA for muxing to multiple external serial devices.

[ Board Design ]:

Please see the IceZero Hardware Design Document and check back for updates.


IceZero is drawn as a 2-layer PCB using CopperConnection from RobotRoom, an excellent PCB drawing tool. Board dimension are 2.57×1.18 inches (65.20×30.02mm) , or the near equivalent outline of a Raspberry Pi Zero.


Top side contains FPGA, SPI PROM, 3 LDOs ( 3.3V, 3.3V, 1.2V ) a OK LED, misc passives and optional 0.100″ PMOD connectors ( 2×6 and 1×6 ) and a single 1×6 0.100″ FTDI header.



Bottom side contains 100 MHz MEMs oscillator, 256Kx16 SRAM and misc passives.


[ Bill of Materials ]

Qty-1 : 220-1572-ND : ICE40HX4K-TQ144 : IC FPGA 107 I/O 144TQFP : $5.77
Qty-1 : 706-1306-1-ND : IS61LV25616AL-10TL-TR : IC SRAM 4MBIT 10NS 44TSOP : $3.36
Qty-1 : 1473-1484-1-ND : SIT8008BI-12-XXE-100.000000G : OSC MEMS 100.0000MHZ LVCMOS SMD : $1.23
Qty-1 : 557-1562-ND : N25Q128A13ESE40E : IC FLASH 128MBIT 108MHZ 8SO : $1.82
Qty-2 : BU33TD3WGCT-ND : BU33TD3WG-TR : IC REG LDO 3.3V 0.2A 5SSOP : $0.28
Qty-1 : BU12TD3WGCT-ND : BU12TD3WG-TR : IC REG LDO 1.2V 0.2A 5SSOP : $0.28
Qty-10 : 1276-5086-1-ND : RC1608J103CS : RES SMD 10K OHM 5% 1/10W 0603 : $0.01
Qty-1 : 1276-5062-1-ND : RC1608J102CS : RES SMD 1K OHM 5% 1/10W 0603 : $0.01
Qty-4 : 1276-2087-1-ND : CL10B475KQ8NQNC : CAP CER 4.7UF 6.3V X7R 0603 : $0.03
Qty-16 : 490-9730-1-ND : GRM188R70J104KA01D : CAP CER 0.1UF 6.3V X7R 0603 : $0.03
Qty-1 : 641-1332-1-ND : CDBU0520 : DIODE SCHOTTKY 20V 500MA 0603 : $0.22
Qty-1 : 160-1176-1-ND : LTST-C170CKT : LED RED CLEAR 0805 SMD : $0.15

Qty-1 : 2×20 0.100″ Straight Female Connector ( PI GPIO )
Qty-2 : 2×6 0.100″ Straight or Right Angle Female Connector (PMOD)
Qty-2 : 1×6 0.100″ Straight or Right Angle Female Connector (PMOD)
Qty-1 : 1×6 0.100″ Straight or Right Angle Male Connector (FTDI)

WARNING : The Micron 128Mb SPI PROM is end-of-lifing from DigiKey, so future builds will use a different PROM. Considering switching to Micron 64Mb N25Q064A13ESE40F or Cypress 64Mb S25FL164K0XMFI010 for cost and availability reasons. FPGA itself only requires 1Mb, everything above that is useful for soft CPU development for code storage. 64Mb at $0.85 is nice compromise.

[ Ordering IceZero ]



Right now, ordering bare PCB fabs is the only method for getting an IceZero board. Click on this link for ordering Qty-3 PCBs for $15  from OSH-Park. If there is interest, I will send Gerbers out for fab in China and could PayPal sell and ship single bare PCBs within the U.S. for maybe $5 – TBD. You may also optionally download the OSH Gerbers or CopperConnection layout files. All files are provided complete AS-IS and are provided under the CERN Open Hardware Licence.

[ IceZero License Statement ]

This project is licensed with the CERN Open Hardware Licence v1.2. You may redistribute and modify this project under the terms of the CERN OHL v.1.2. (

[ FPGA Programming ]

The Python script may be used for downloading a Lattice PROM file into the SPI PROM from a Raspberry Pi.  This PROM utility is available on GitHub.

[ SUMP2 Sample Design ]

A SUMP2 Verilog sample design for the IceZero is available on my Dropbox. This uses the same Pi software as SUMP2 for IcoBoard.  A very important feature of the IceZero sample design is that it may be used with zero FPGA experience as both a Logic Analyzer and a generic GPIO port expander, providing 24 software defined pins for things like reading switching, driving LEDs and even PWM outputs for servo control.


IceZero FPGA Board for RaspPi

SUMP2 100 MSPS 32bit Logic Analyzer for icoBoard+RaspberryPi

2016.12.22 : After publishing SUMP2 96 MSPS Logic Analyzer for $22 iCEstick, BML was contacted by the icoBoard team in Austria inquiring the feasibility of running SUMP2 on their Lattice FPGA on the icoBoard and the RaspberryPi. BML was up for the challenge and has successfully ported the Windows + iceStick SUMP2 to work on Linux on Pi + icoBoard. This post describes how to configure the RaspberryPi and icoBoard to be a standalone 32 channel 100 MSPS logic analyzer.

File Download Area ( BML’s Dropbox ):

Note: See BML’s GitHub also

What is needed:

  1. A Raspberry Pi Model3 ( or faster ), a USB mouse and a HDMI display.
  2. An icoBoard from
  3. Free open-source software and firmware for SUMP2 from Black Mesa Labs.

Step-1 ) Download the 2GB custom Jessie-Lite image. Full details on this image ( and how to recreate from scratch if desired ) are available here. This image is a console only Linux that has Python modules pre-installed and a boot mechanism for installing files from a AppData.tgz file on a USB stick. Users may choose to manually install contents of AppData.tgz on their existing Linux Pi images, but no support for this is offered by BML.

Step-2) Burn the 2GB image to a uSD card using Win32DiskImager or similar tool. Warning – if you use a 2GB card, it might not work if it has fewer sectors than the 2GB card used in the generation of the image. Recommend using a 4GB uSD just to be safe.

Step-3 ) Boot the Pi with the new card.  It should boot up to a “Hello World” message.

Step-4) Download and Copy AppData.tgz and install_software.txt files from BML to a USB flash drive’s root directory.

Step-5) Boot the Pi with the USB flash drive. It should now install and launch the SUMP2 GUI.

Step-6) Configure the FPGA PROM by right-clicking in the waveform area of the screen ( not the signal name area ) and select System, Load_FPGA.  After this has completed, right click again and select System,Reboot. Remove the USB stick to prevent software from re-installing on the next boot.

Step-7) After the reboot the SUMP2 firmware and software should be fully functional.


[ About the design ]

bml_sump2_on_ice_stick (1).png

SUMP2 is entirely open-source hardware ( Verilog RTL FPGA design ) and open-source software ( Python GUI ).   The open-source Hardware and Software design files for the icoBoard version are all available here.  Please read the original SUMP2 for iCEstick blog for more detailed information on SUMP2. The icoBoard version uses a Lattice iCE40HX8K which roughly has 8x the FPGA fabric resources as the iCE401K on the iCEstick. Instead of using asynchronous 1 MHz serial communication ( FTDI 921,600 baud over USB ), the icoBoard uses the Raspberry Pi’s built in SPI interface running at 32 MHz. Both versions of SUMP2 use Mesa Bus Protocol for transferring 32bit virtual PCI write and read cycles over serial interfaces. for icoBoard communicates directly with the hardware, unlike for used TCP sockets for communication to as a hardware/software abstraction layer. Setup for SUMP2 on icoBoard is much easier as the open-source nature of the Pi platform allows BML to design for a walled garden environment ( made completely of open-source mind you ). BML provides the OS and the Application and the user provides the hardware of which there is a single choice, icoBoard and a Pi Model 3. Only variable to test for is differing HDMI screen resolutions.


[ PMOD Pinouts ]

Screenshot at 2016-12-25 18-11-03.png

The icoBoard has 4 0.100″ 2×6 PMOD connectors labeled P1-P4. Each connector is 1 of 4 byte inputs to SUMP2 for LVCMOS 3.3V signals.  P1 corresponds to events[7:0], P2 events[15:8], P3 events[23:16], P4 events[31:24].

[ SUMP2 on a small HDMI Display ]


Large LCDs are fantastic, but if you want a small footprint dedicated logic analyzer to sit next to your bench scope, SUMP2 can do that too. With the exception of optional signal renaming, the SUMP2 software interface is entirely mouse driven, no bulky keyboard required to operate. No Linux login required. SUMP2 boots and runs like an oscilloscope – OS is completely in the background, hidden from the end user ( but absolutely still available to them for tinkering ). The final BML setup for SUMP2 on icoBoard uses a small 7″ 800×480 LCD and the Pi+icoBoard easily attaches in the rear with some doubled sided velcro tape. Although the standard Linux text console (shown above) is much too small to read at 800×480 on 7″, the SUMP2 menu option Misc,Font_Larger or Font_Smaller allows for changing font size on the fly to make for a compact and readable display (shown below).  Note that this setup uses the -bundle option in the sump2_wave.txt file to group multiple signals into a single “bus” that is then displayed as hexadecimal instead of a binary waveform. More details are available in the file sump2_manual-txt.

File_000 (1).jpeg

[ Executing from USB Flash Drive ]


BML opted to execute the SUMP2 software from an external USB stick instead of the on board Pi uSD card. To accomplish this, simply copy the folder ~/AppData to /media/usb0 ( or do this from a PC ).  The advantage of running SUMP2 from USB is that transferring screen captures ( PNG, JPEGs ) and VCD exports from SUMP2 from the Pi to a PC much easier. If running SUMP2 with only a mouse ( no keyboard ), signal renaming is still possible by removing the USB stick with the Pi off and manually editing the ./AppData/sump2_wave.txt file using Vi or similar editor prior to booting the Pi. Configuration of the GUI is all clear text within sump2.ini and sump2_wave.txt files.

[ Flying lead adapter to PMOD ]

For just $1, this PCB may be ordered from OSH-Park that labels and adapts a PMOD connector to signal and ground pair 0.050″ pitch vias for making a flying lead adapter with dedicated signal ground returns for optimal signal integrity.


A slightly different version available here instead breaks out the PMOD to a 1×8 0.100″ row along with a single GND pin and 3V pin suitable for slow signals and dupont cables.


This PMOD2PMOD board allows 2 PMODs Masters to plug into each other, for example 2 icoBoards can interact with 2 of these for 16 IOs between them. Useful for using SUMP2 on one icoBoard for debugging another FPGA design. 3V are not connected, only signals and grounds. Note that the signals are twisted 0->7, 1->6, etc and should be untwisted in the FPGA fabric.


[ Making PMOD inputs 5V Tolerant ]


The PMOD inputs of the icoBoard are 3V only and are NOT 5V tolerant. Since both the iCEstick and icoBoard use the same PMOD connectors, the 5V tolerant input adapter designed by BML for the original SUMP2 on iCEstick may also be used on the icoBoard. The bare PCBs may be ordered at this link direct from OSH-Park for $5.  With the bare PCB, a simple 2×6 0.100″ right angle male header and a DIP SN74LVC244AN may then be soldered to provide a 3V input to icoBoard that is also 5V tolerant.  Total cost of parts and PCBs for 3 PMOD connectors total is only about $10. WARNING: Care must be taken not to configure the FPGA GPIO features as outputs to prevent damaging the FPGA. By default, the FPGA powers up with PMOD pins configured as inputs, allowing safe operation with this adapter.

[ GPIO Feature ]


But wait, there is more.  The Lattice iCE40HX8K FPGA on the icoBoard has 8x the resources of the iCEstick, so along with the SUMP2 logic analyzer engine, the FPGA design also includes 8 PWM ( pulse width modulators ) and GPIO ( General Purpose Input Output ) capabilities for all 32 PMOD signals.  Completely unrelated to SUMP2, this feature bundled in the same FPGA bitstream may be used as a general purpose port expander for the Raspberry Pi.  With time-multiplexing, the design actually supports controlling 32 RC servos ( only 8 in motion at once ).  By default, the GPIO portion of the FPGA design powers up with a 32 PMOD signals as inputs, allowing SUMP2 to operate on external signals without programming the GPIO registers. Refer to the ./source/reg_space.txt file for detailed register descriptions on programming the GPIO module. The example file included in AppData.tgz demonstrates how Python and Mesa Bus Protocol can be used for configuring the GPIO features. Conversely, the SUMP2 FPGA bitstream may be used without ever using SUMP2 if a Pi user simply wants to add more IO capabilities to their Pi.  Look for future GPIO FPGA only design from BML for the iCEstick that may be used for bit-banging any 3V device from a PC using Python ( including writing and reading SPI and I^2 PROMs ). $22 makes for a very nice platform for controlling devices and monitoring switches from any PC with a USB port.

[ Built in Self Test (BIST) Feature ]

The GPIO feature of the FPGA design and the included software may be used to drive test stimulus to all 32 PMOD pins.  This feature is useful for testing that all the SUMP2 software and hardware is operational. The electronic stimulus is provided by the SPI interface between the FPGA and Pi and the 8 PWM units.  WARNING : Enabling this feature drives the test data as FPGA outputs to the PMOD connectors, so it is important that nothing be connected to them ( including the 5V to 3V translation boards ). Running which enables all the output buffers of the FPGA may damage the FPGA if other devices are also driving the PMOD pins. Only run if you are certain nothing is electrically connected to the PMOD pins.

Step-1 ) From SUMP2 GUI, select System, Quit.

Step-2 ) From Linux command line, type %python   ( Configs GPIO outputs )

Step-3 ) From Linux command line, type %source   ( relaunches GUI )

[ Demo at 33C3 ]

Clifford of demonstrated SUMP2 running at the 2016 Chaos Communication Congress (33C3) festival in Hamburg Germany.

A post shared by Clifford Wolf (@cliffordvienna) on


[ In Closing ]

Please enjoy SUMP2, a 32 channel 100 MSPS open-source logic analyzer for icoBoard and RaspberryPi.  Follow BML on Twitter for updates on SUMP2 and other open-source software and hardware projects from Black Mesa Labs.


SUMP2 100 MSPS 32bit Logic Analyzer for icoBoard+RaspberryPi

SUMP2 – 96 MSPS Logic Analyzer for $22




2016.22.22 : SUMP2 now also available for RaspPi+icoBoard here.

2016.12.13 : Great video on SUMP2 from Bil Herd at Hackaday.

2016.10.31: Thanx to SteveDC, a 3D printed case is now available for SUMP2 here.

2016.10.30 : SUMP2 5V Input shield is now available from OSH-Park for $5. BML can also design similar shields for RS232,RS422/485,LVDS and CAN Bus if there is any interest.

2016.10.24 : Black Mesa Labs has an ongoing mission to develop easy to use and fully capable open-source hardware and software tools that make engineering electronics easier. One such tool is this new low cost open-source logic analyzer called SUMP2 for people who otherwise work in the blind without an oscilloscope or logic analyzer on their bench top.  BML’s 1st incarnation called SUMP1-RLE in 2014 was a 16bit FPGA based logic analyzer that performed real-time hardware compression and decompression. The decompressed data was streamed out over USB using the open SUMP protocol ( hence the name ), allowing it to be used with the excellent Java software from the original 2007 project. The SUMP1-RLE project was later enhanced from just 16 triggerable events to also include 2 DWORDs of “data” ( additional 64bits of non-triggering non-compressed signals ) and advanced triggering options. Including the data DWORDs made SUMP1 a useful tool for complex FPGA development debugging of internal FPGA event nodes and data paths. These new features required new custom software, written by BML in .NET for Windows. The software was functional, but graphically slow and was mostly used for trigger setup and then exporting captured data as VCD files into GTKwave for viewing. SUMP1 also did not scale in width, depth or time, it was fixed at 16 events, 2 DWORDs and a 2^20 timestamp ( 1 Million Samples ) both in hardware and software. In 2016 BML decided to do a complete start-over on the SUMP RLE concept and developed SUMP2-RLE ( or just SUMP2 for short ). New Hardware, New Software. More features, better scaling – introducing SUMP2:


The sump2.v verilog file is designed to work inside any FPGA or ASIC containing block RAM and scales in complexity from 1-4 bytes of events ( 8-32 triggerable and RLE compressible signals ) and 0-16 DWORDs of up to 512 non-compressed data bits. Depth and width of RAM scales on instantiation to best fit a wide range of FPGA technology. The full featured SUMP2 configuration is designed to be used on internal nodes within very large $100 – $1000 FPGAs. In this configuration for analyzing internal FPGA nodes it is very similar to proprietary FPGA vendor solutions such as Xilinx ChipScope and Altera SignalTap. SUMP2 has the advantage of being fully open and also offers RLE compression that can offer 10x – 1000x the time storage of similar FPGA logic analyzers not aided by hardware compression. Duty cycle hardware applications such a pulse-echo radar can readily achieve 5,000x compression using the new RLE engine with 2^32 timestamps. The scalability of SUMP2 also permits it to work in ultra low cost ( sub $5 ) FPGAs such as the Lattice iCE family. The Lattice iCEstick eval board at only $22 with included FTDI USB interface and PROM programming provides for a perfect SUMP2 platform for electronic debugging of Arduino and Raspberry Pi like projects involving 3V serial ports and GPIO. Communication between hardware and software over USB is all done using the Mesa Bus Protocol , an open serial protocol for transferring 32bit PCI reads and writes over UART, SPI and SERDES serial links between computers and FPGAs.




To fit within the iCE40HX1K FPGA, sump2.v verilog RTL design is instantiated for 16 input events, no DWORDs and 1k depth of RLE capture RAM sampling at 96 MHz. The graphical backend software is, a PyGame application used for arming the hardware and dumping and displaying the capture for analysis. Compared to the SUMP1 .NET app, the PyGame SUMP2 version is very fast. Although supports exporting and importing VCD files, it is entirely not necessary to use a standalone VCD viewer such as GTKwave or Modelsim.

A simple example of a Unit Under Test.  Below pictured is a 10 MHz ( 100ns period ) oscillator driving a 74ACT161 4bit counter with a 74HC08 AND gate on the d(2) and d(3) upper bits of the counter. A push button switch to ground with a 10K pullup resets the counter. 8 nodes of interest are connected via Dupont ribbon cable to the iCEstick PMOD header.


Short demonstration video of the PyGame application:

The initial full capture of the reset button being released. The capture represents 4168 samples at 96 MHz using only 1K of RAM by utilizing RLE compression. RAM is hard partitioned 50/50 pre and post trigger.sump2_0003.png

SUMP2 has the ability of masking input events prior to arming which allows for greater RLE time compression. By double-clicking and “Hiding” the clk_10m signal prior to a new acquisition, the highly active clock signal is masked. This next capture without the 10 MHz clock is twice the length, or 83uS.  Also notice the very short reset switch bounce captured. Masking the LSB counter bits would further increase total capture time.


Mouse scroll wheel can be used for zooming in and out in time, allowing for rapid detailed analysis and cursor measurements.


Right-Clicking the mouse launches popup menus for tool selection.


The left side popup allows for selecting a signal and then assigning it as a rising or falling edge trigger.


Steps for building your own open-source SUMP2 Logic Analyzer for the Lattice iCEstick.

What is needed:

  1. $22 iCEstick from Mouser, Digikey or direct from Lattice. ( ICE40HX1K-STICK-EVN )
  2. Free FPGA Diamond Programmer software from Lattice.
  3. Windows Device Driver for the FT2232H USB chip from FTDI ( this may also be included with Lattice Programmer ).

and this free stuff from Black Mesa Labs:

  1. Bitfile for SUMP2 for the Lattice iCE40HX1K FPGA.
  2. – a Python TCP server for communicating to hardware over USB.
  3. – a Python PyGame application. Handles triggers and waveform viewing.
  4. FPGA Design Files ( Optional, only needed if not using prebuilt Bitfile ).
  5. 5V Input shield PCB design in CopperConnection ( Optional ).

And finally, a bunch of text file documentation from Black Mesa Labs:

  1. Installation Instructions
  2. FAQ
  3. Program Launching instructions
  4. Troubleshooting guide
  5. Pinout for connecting flying leads to iCEstick
  6. Change Log for Software and Hardware
  7. Bug Report

EE Times Article by Clive “Max” Maxfield on SUMP2

Hackaday Article by Jenny List

Please enjoy SUMP2, a 96 MSPS 16bit 3V logic analyzer for only $22. Follow BML on Twitter for updates on SUMP2 and other open-source software and hardware projects from Black Mesa Labs.


SUMP2 – 96 MSPS Logic Analyzer for $22

Easy path to running embedded Python on a RaspberryPi


10.14.2016 : Fixed the ZIP file for the Jessie-Lite disk image. 1st one was an invalid zip.

10.09.2016 Black Mesa Labs is a huge fan of both the Arduino community and the Raspberry Pi community.  Arduino’s make it really simple to do embedded tasks that don’t require a ton of horsepower ( flashing LEDs, etc ) where-is the RaspberryPi platform provides the full power ( and complexity ) of a complete Linux workstation for as little as $5 ( Pi Zero ).  Unfortunately, embedding a $5 Linux workstation isn’t always what you really want to do. You want to embed software into something like an Arduino that you apply power to and it then does something pre-programmed, no mouse, no login, no screen or keyboard required.  Wouldn’t it be great for non-SysAdmins to have a easy to use RaspberryPi solution for booting Linux and running a single predetermined piece of software like an Arduino does? Keep reading, Black Mesa Labs has a solution…

BML has created a custom Raspbian Jessie-Lite image for booting and executing a single application easily. This Pi image was used for the HAB1 balloon ascent to 31km (103,000 feet ) in April of 2016.  At the start of the project BML realized the amount of software required in the limited time for the flight just wasn’t possible writing embedded C/C++ code.  At BML the most precious resource is engineering time, therefore software projects tend to be written in Python whenever possible as the time overhead for writing, compiling, downloading and testing C and C++ is a tremendous hindrance. BML efficiency and quality of software using Python is easily 10x that of C/C++ ( and don’t get me started on writing and debugging Assembly language ).


This post is the detailed description of creating this 2GB Pi image for embedded Python that anyone is free to either create or just download ( from above dropbox link )  and image on their own Pi SD card.  Running custom software ( Python text based, or PyGame full graphical ) is as easy as copying a single Python file to a USB stick and then turning the Pi on.  This image is designed to work headless ( no screen – as was used in HAB1 ), or optionally with a HDMI display, or a 3.5″ 480×320 TFT display from either AdaFruit or Kuman.

The brains of the operation is this single file boot_script-sh containing 70 lines of BASH scripting that executes on powerup and behaves like a PC’s BIOS boot sequence of boot from A:\ ( Floppy ), D:\ ( CD-ROM ) and then finally C:\ ( hard drive ).  The BML attempts to execute from a NAS ( Network drive ) 1st, then from the USB stick and finally from the SD card looking for special pragma files on what to do.  It also automates software updates by auto de-tarring ( unzipping ) *.tgz or *.zip files from a USB stick to the SD card.  In short, you can write some Python on your PC ( or Linux workstation ) , copy it to your your USB flash drive, stick it in your Pi and your Pi will run it automatically on boot. Streamlined and efficient, right?


This post ends with a detailed list of instructions on configuring an off-the-shelf Raspbian Jessie-Lite image for this automated behavior.  Look for an example PyGame application soon from BML that fully utilizes the Pi camera and TFT touch screen display in an example embedded camera application.


[ Download 2GB PiTFTr Jessie-Lite image from Adafruit ]
Minimal image based on Debian Jessie for Pi 1,2,3
Release date:2016-03-25
Kernel version:4.4.23+

[ If using Kuman display, download and burn 2nd card from Kuman CD-ROM ]
Copy 2 files from Kuman Image to Adafruit Image:

Select display to use by changing line in /boot/config.txt
WARNING: If not using TFT display, line MUST be commented out
(Note: This can be done from Windows as /boot is FAT partition )
From: dtoverlay=pitft35r : For AdaFruit 3.5″ TFT Display
To: dtoverlay=tft35a : For Kuman 3.5″ TFT Display
To: #dtoverlay=pitft35r : For regular HDMI Display

[ 1st Boot : Login pi,raspberry ]

[ Configure Raspbian ]
sudo raspi-config
1) Expand Filesystem to fill 2GB card.
3) Boot to Command Line. B2=Console AutoLogin as pi
4) Wait for Network on Boot. YES
5) International
Locales : Deselect en_GB.UTF-8 UTF-8
Select en_US.UTF-8 UTF-8
TimeZone : US Pacific-New
Keyboard : Generic 104-key PC, English-US
6) Enable Camera Interface = YES
9) Advanced Options
A2 : HOSTNAME : RaspPi
A4 : SSH : YES
A6 : SPI : YES
A7 : I2C : YES
A8 : SERIAL : NO ( Don’t allow serial port login )
A9 : AUDIO = AUTO ( vs Force HDMI or Force 3.5mm )

[ Reboot and run /sbin/ifconfig to get IP Address ]

[ ssh -l pi ( password raspberry ) from normal desktop ]
Note: May be necessary to delete ~.ssh/known_hosts file

[ Running script automatically after login ]
sudo vi /etc/profile
Add the following line to the end of the file
. /home/pi/

[ Enable Mounting USB Drives ]
sudo apt-get install usbmount
sudo vi /etc/usbmount/usbmount.conf and modify line: ( Makes USB Writable )

[ Enabling tmpfs – Writing temp files to RAMdisk instead of SD Card ]
sudo vi /etc/fstab
tmpfs /tmp tmpfs defaults,noatime,nosuid,size=100m 0 0
tmpfs /var/tmp tmpfs defaults,noatime,nosuid,size=30m 0 0
tmpfs /var/log tmpfs defaults,noatime,nosuid,mode=0755,size=100m 0 0
tmpfs /var/spool/mqueue tmpfs defaults,noatime,nosuid,mode=0700,gid=12,size=30m 0 0
# Unable to reboot or shutdown. “Failed to talk to init damoen”
# tmpfs /var/run tmpfs defaults,noatime,nosuid,mode=0755,size=2m 0 0

[ Mounting BlackMesa NAS ]
mkdir /home/pi/nas
sudo vi /etc/fstab
//BlackMesa/khubbard /home/pi/nas cifs auto,uid=1000,gid=1000,username=khubbard,password=password,rw,file_mode=0666,dir_mode=0777 0 0

[ Allow users to modify /boot/config.txt without sudo (for force_hdmi things) ]
#/dev/mmcblk0p1 /boot vfat defaults 0 2
/dev/mmcblk0p1 /boot vfat users,rw,owner,umask=000 0 2
[ Installing PyGame for Jessie-Lite ]
sudo apt-get install rpi-update
sudo rpi-update
sudo apt-get update
sudo apy-get install python-pygame
sudo apt-get install python-picamera

[ Install MP4Box for Converting H264: MP4Box -add filename.h264 filename.mp4 ]
sudo apt-get install gpac

[ Speech Synthesis w/o Internet Connection ]
sudo apt-get install espeak
espeak -ven+f3 -k5 -s150 “I’ve just picked up a AE35 fault ” 2>/dev/null

[ PySerial ]
sudo apt-get install python-pip
sudo pip install pyserial

[ SPI Serial spidev ]
sudo apt-get install python-dev
sudo apt-get install git
git clone git://
cd py-spidev
sudo python install

[ RockBlock Sat Modem ]
sudo apt-get install screen
sudo apt-get install usbutils
git clone

[ Schedule a fsck at next reboot ]
sudo touch /forcefsck



Easy path to running embedded Python on a RaspberryPi

1″ 100W Hot-Plate for SMT Reflow



Black Mesa Labs has been using a $20 hot plate for a year now for soldering QFN ICs to PCBs using the BML Inverted Solder Ball reflow technique. This works great for soldering 0.5mm pitch QFN and LGA type packages that would otherwise require messy stencils and paste. Only issue so far has been the size ( 10″x10″x3″ ) and thermal mass of the commercial hot plate as it consumes precious microscope work area and unfortunately stays quite hot for 30+ minutes after a quick 4 minute single IC reflow job.  BML boards are mostly 1″x1″, so a 800W hot plate with a 6″ diameter heating surface is overkill for most jobs.


Wanting something much smaller for a typical BML PCB – stumbled across this 24V DC heating element on Amazon for only $14. It is rated for 24V at 5-7 ohms ( or 4.8Amps ).  A surplus 19.5V DC 5A laptop power brick laying around BML seemed like a perfect match for this element.  BML has safety rules avoiding designs above 48V – so the 100Watt 20V DC supply coupled with the 24V element seemed like a great way to make a lot of heat in a small surface area in a short amount of time.


First experiment was to see if this little element would reach +200C in under 4 minutes. Not wanting to cut up the laptop supply’s power connector – located this


power connector adapter for only $5 and cut off the yellow Lenovo end of it and converted it to 0.100″ spaced Dupont connector instead. Hooked up a simple push button switch in line with the circuit – pressed the button and measured surface temperature with a digital thermometer – reached 200C in only 90 seconds!  Too fast for reflowing 40nm FPGAs unfortunately. Wanting to keep the 20V supply – needed to switch to pulse width modulation to slow down the thermal ramp to closely match solder reflow profile of 4 minutes to +200C. A relay? Nah – lets design a custom PCB with power FETs!


After consulting with BML’s “all things analog expert on retainer” DP on how best to switch 100W at 20V – designed a small $2 2-layer PCB as a low-side switch using two IRLML6344TRPBFCT-ND 30V Power MOSFETs in parallel.  Design was drawn ( no schematic ) straight in CopperConnection Gerber drawing tool in less than 15 minutes and fabbed by OSH-Park in about 2 weeks for $2 for a ~1″ x 0.5″ 2-layer 0.8mm PCB.


Rds On for this N-FET is 0.029 ohms at 5A ( or  725 mW ) which is near the 1.3W limit for the itty bitty SOT23 device. Not having any heatsinks other than the connection to the PCBs giant “Drain Plane” – opted to share the 5A load across two FETs in parallel. The N-Channel MOSFET’s Source is technically ground – but all the heat is dissipated through the Drain, so large pours on both PCB top and bottom were made to better dissipate the Rds On heat. Design is feed thru for + and – from the supply to the + and – for the load even though the + supply doesn’t touch the circuit at all.  Placed 3 different sized vias 0.125″, 0.079″ and 0.040″ so the board may be easily reused for other projects of various gauge wire needing high voltage and current switching.  A 100K resistor to GND ensures the FETs don’t turn on by themselves without a driver present (powerup Hi-Z) and a 1K series resistor to the Gate of both FETs limits the in-rush current. These Infineon  N-Channel FETs are only $0.29, come in a small SOT-23 package, can switch 5Amps from a 3V LVCMOS signal and are now BML’s go to device for power switching.


Above is a Owon Scope capture of the FET turn on time ( Gate versus Drain ). CH2 ( Yellow ) is the Gate of the N-FET which is driven by LVCMOS 3.3V totem-pole from an AVR through a 1K series resistor. It takes 500ns for the Gate to go from 0V to 1V and then the FET turns on.  CH1 (Red ) is the Drain transitioning from pulled up ( via 1K thru the LED ) to clamping to GND. This transition takes about 2uS total.



An Arduino Pro (above) was chosen as the PWM controller.  Most BML CPU designs are either RaspPi or Arduino-Zero based ( ARM 32bit ), but BML had this old Sparkfun board in a box and it was the right dimensions as a mechanical base for the project. The 1.5″ diameter heating element is suspended about 1″ in the air, so the wide 2″x2″ Pro board keeps everything from tipping over.

Above picture shows everything cobbled together. A small piece of aluminum foil is wrapped around the element to keep flux from making a mess of it while under reflow. The heating element comes with 22 AWG solid wire crimped to it and extending about 2″ away. The wires are soldered to a 1×2 SIP connector which then mates to another 1×2 SIP connector on the FET board ( being able to remove the heating element from the circuit while under development was VERY important ).  The FET board is placed in the center of the Arduino Pro board atop some poster putty and held in place with the Enable wire (White ), the 1,500 resistor voltage drop network and a ground wire. The Pro can be powered from an FTDI USB cable of course, but to power it from the single Laptop supply, the voltage required dropping down from 20V to around 12V for the on board LDO.  Three 500 ohm leaded resistors each provide about a 2V drop while the AVR CPU is sipping 4mA, for a total drop of around 6V. A large 1K resistor provides 20mA to the red LED whenever the FET gates are turned on and the heating element is getting power.  Total cost was under $20 for the project – not counting the Arduino Pro in the junk box.MLX90614(E,K)SF-xxA.JPG

The Arduino was chosen over an FPGA as the PWM rate is really slow ( seconds ) and the Arduino makes it easy to expand the design and eventually interface to a Infrared Thermometer over I2C via existing tutorials and libraries.  Eventually the design could be expanded to measure the temperature at the surface of the FR4 under reflow for either reporting and / or control.  For now – the dead reckoning PWM method is plenty sufficient.  As the heating element contains very little thermal mass – it cools down in just seconds.

Above is the target solder reflow profile and below is the achieved profile as measured with a thermocouple on a scrap 1″x1″ FR4 PCB.

The GPL’d open source C++ source is available here hot_plate and is fairly straight forward.  When the button is pressed, the AVR starts a 4 minute PWM state machine that gradually increases the PWM duty cycle from 30% to 40% to 60% and then off.  Measuring a scrap piece of FR4 with a thermocouple mounted to it, an ideal reflow profile of 20-150C for 90 seconds, 150-200C for 90 seconds and finally 200-250C for 50 seconds was achieved. Pressing the button mid thermal cycle cancels the cycle. The AVR and giant Pro board is definitely overkill – but the PCB size made it a great platform to mount everything else to.

A word on safety – although this project is under 48V – the amount of heat it can generate could definitely start a fire if powered up in the wrong place ( under a stack of old newspapers for example ) .  To prevent any potential small fires from starting 3 levels of safety were built it. 1) the Arduino runs the heat profile only when the pushbutton is pressed and then automatically turns itself off after the profile time is complete. 2) The 20V 5A power to the electronics goes through a toggle switch. 3) The original laptop barrel connector is quickly and visibly disconnected from the setup when reflow is complete allowing the hotplate to be visibly disconnected from the power supply when not used.

Below is a YouTube video of a Lattice ICE5LP4K-SGN48 FPGA reflowing on the “Mesa Logic DIP” PCB using the BML Inverted Solder Ball reflow technique. This is a general purpose FPGA board on a 0.100″ grid providing 24 user IOs in a 0.600″ x 1.6″ package. This board has a destiny to reach 100,000 feet (~30km) this coming May as a HAB controller for a weather balloon. It will communicate with both an “on balloon” Raspberry Pi and with a ground station via a RockBLOCK Iridium satellite modem using Mesa Bus Protocol. Stay tuned to Black Mesa Labs for an upcoming blog on all the details of the custom HAB electronics.



1″ 100W Hot-Plate for SMT Reflow

Mesa Bus Protocol


Enclosed text file ( mesa_bus  ) is the open-source  Mesa Bus Protocol for transferring bytes between CPUs and FPGAs. It is intended to transfer data between 50 Kbps up to 10 Gbps over UART to SERDES links with just a few wires and very little hardware overhead. It is a very small gate foot print byte transport protocol for encapsulating and transferring payloads of higher protocols (0-255 bytes per payload). Think of it like a cross between Ethernet and USB 3.1. The advantages Mesa Bus Protocol has over USB, Ethernet and PCI is that it fits easily within a $3 FPGA and may be bus mastered either by a PC with a FTDI cable or any old ARM/AVR Arduino CPU (or RPi) with just two standard UART serial port pins. As it is ASCII based, Mesa Bus Protocol is also very portable to wireless devices such as Bluetooth SPP and the RockBLOCK satellite modem for the Iridium network .


Have you ever placed a regular envelope inside an interoffice envelope? Mesa Bus is that interoffice envelope. Where Ethernet transfers UDP, TCP, HTTP,etc packets without higher level knowledge – Mesa Bus can transfer SPI, I2C, Digital Video, 32bit LocalBus,etc  from chip to chip without protocol knowledge.  Mesa Bus works with up to 254 devices with only 2 wires between each device. Black Mesa Labs currently uses Mesa-Bus with the Mesa-Logic MCM FPGA and BD_SHELL.exe windows executable, Python, or an Arduino-Zero ( ARM ) as bus master. Payloads have been digital video ( 800×600 at reduced frame rates over a 40 MHz synchronous Mesa Bus link ) and 32bit local bus write and read cycles (PCI-ish) to FPGA registers and also for FPGA flash firmware updates. Mesa Bus Protocol fully supports prototyping embedded software 1st on a PC in a rapid scripting language like Python as it is clear ASCII that may be transported over a standard FTDI cable or Bluetooth SPP connection.





Mesa Bus Protocol

Quick and Easy Fence Post Replacement


Taking a short break from electronics to document an easy solution for the frustrating home repair of rotten fence post replacement.  Here in Seattle, it is quite common for pressure treated 4×4 fence posts to rot from the ground level down after about 20 years in the humidity. Standard replacement method is to dig out and smash up all of the 24″ concrete base surrounding the rotten 4×4 and replace with new concrete. Two feet ( ~1/2 a meter ) down is a lot of digging ( especially in Seattle clay+rock soil ) and with 3 rotten posts ( and 27 more most likely to fail in the next 5 years ) – I set out on an engineering mission to find an easier – greener – way. This might not seem appropriate for a Black Mesa Labs post – but just like how BML does things very different in electronics from society norm ( example : soldering 45nm QFN FPGAs onto 2-layer PCBs using a $20 hot plate ) – the fence post removal was a full Thomas Edison obsession of doing something different through persistent experimentation. Going into this project I was told by countless people 1) That just isn’t how it is done, 2) It won’t work and 3) Just hire a guy to take care of it. Like all things at Black Mesa Labs,  I was determined to do things different.

Through much trial and error – this is the Black Mesa Lab “Cork Popper” method of fence post removal and replacement without all the digging. This method supports removing the rotten section of 4×4 while retaining the majority ( 75%) of the existing concrete base in place. Keeping the existing concrete also means the new post will be in the same location and plumb as the previous post. Less waste, less effort, faster repair.

Step-1 ) Tear down the fence sections supported by the rotted 4×4 post. A Sawzall with a metal cutting blade that rips through nails makes quick work of this.


Step-2) Dig a hole 12 inches ( 1/3 meter ) down around just two side of the concrete base. This is only 1/2 the depth of the entire concrete base. Once exposed, this concrete will now be like an egg-shell ( assuming it has been in the ground for 20 years ). The packed earth is the only thing holding this structure together at this point in time. Using a wrecking bar and a small sledge ( or even just a hammer ) – pry off the exposed concrete. It should easily break off with very little effort.



Step-3) Post Extraction.  With the concrete removed, the post is now much easier to extract as only the very bottom 12″ is applying pressure against all 4 sides.  If the post is not entirely rotten, the easiest method is to drill a 3/4″ hole through the post above ground level and shove a segment of 1/2″ black iron pipe.  For less than USD $40 total I purchased two matching 6 ton hydraulic bottle jacks which can then lift the iron pipe ( and 4×4 post ) slowly out of the ground.


Step-4) Is only necessary if Step-3 failed – the post is so rotten that it breaks into 2 pieces, a 6′ above ground section and a 2′ below ground section.  Using a small hand saw ( such as this great little folding jab saw ) – or an awesome mini “Sawzall” such as this 12V Bosch reciprocating saw cut the rotten section away and leave a nice level 4×4 surface of fairly decent wood. A friend of mine says this 12V Bosch is actually made by Playskool , but I don’t care – it gets into really tight places. Trick is to have lots of 12V Lithium Ion batteries ( I have 5 ).


Step-5) Attach the extractor. I built this extractor for about $40 using these 12″ lag bolts and some eye bolts from Home Depot and this 5,000 lb 36″ trailer safety chain. I have 30 posts total in my fence – so money well spent. Extracting the old 4×4 in tact means I can reuse 75% of the existing concrete base. This is about 150lbs of concrete I don’t need to buy, haul and mix and old concrete I don’t need to dig out of the ground and toss into a land fill.  Win-win.


Step-6) Screw the extractor into the remaining section of post using a ratchet and then lift it out using the bottle jacks.


Step-7) Insert the new post. I used Hem-Fir Severe Weather Standard Pressure Treated Lumber (Common: 4 x 4 x 8; Actual: 3.5625-in x 3.5625-in x 96-in) from Lowes for $10. The 4×4 post should go in easily assuming dry wood and should already be plumb ( but check with a level ). Pounding with a 4lb sledge from the top if necessary. I really like this 4lb sledge as it is small enough to wield on top of a 6-foot ladder like a normal hammer but still packs a punch. For the old/new hybrid base, surround the exposed 4×4 with some chunks of 4x4s or 2x4s as temporary spacers and then surround those with some cardboard. Fill in outside with packed dirt. Remove the wood blocks and pore the concrete between the post and the cardboard. I used a single 80lb bag of concrete for 2 posts. I think next time I will buy 50lb bags instead as the 80lb bag is just awkward to handle. While the concrete sets – remove old nails from the fence panels and then start rebuilding.  I rebuilt using these Deckmate star drive screws and my Bosch Impact Driver. Very little effort and time compared to hammering and will make the next tear down job much easier. Hopefully this post will last another 20 years.

12 hours of work start to finish and the Job is done!

I hope you found this short tutorial on a quick and easier method of fence post extraction and replacement helpful.

Quick and Easy Fence Post Replacement