BML S7-Mini FPGA Module

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2019.05.19 : This blog posting is about the open source S7 Mini FPGA module designed by Black Mesa Labs and professionally manufactured and distributed by Trenz Electronics.  In short, it is a Xilinx Spartan7 7S25 on a 1″x2″ module with 64 Mbits of DRAM, Config PROM, 5V single supply solution and provides either 32 user I/Os on a 0.100″ (2.54mm) DIP grid or 64 user I/Os on a 0.050″ (1.27mm) grid at LVCMOS33 levels. This posting isn’t complete, but a work in progress and central point for links to example GitHub designs, purchasing links, schematics, etc.

S7-Mini Purchase Options :

  1. Direct from Trenz – warning – DHL shipping to US can be pricey ( $50 ).
  2. From Trenz partner Mirifica who will ship via low cost standard post.
  3. TBD Digikey in the future.

What else to buy:

  1. Digilent HS2 JTAG Programmer. $60 from Digikey here.
  2. FTDI 3V USB cable TTL-232R-3V3. $20 from Digikey here.

Schematics :

  1. Direct from Trenz website.
  2. Copy from Black Mesa Labs GitHub here.

I’m just getting started on this blog. It will detail multiple sample designs for the S7-Mini on my S7 Mini GitHub here. Simple Hello World” blinky light and finally the DeepSump 32/64 channel 200 MSPS logic analyzer which captures to 64 Mbits of DRAM.  I’m doing this 100% on my free time, so it might take be a bit to finish this blog posting, but it is my #1 Black Mesa Labs project.

[ History of the S7-Mini ]

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The S7 Mini began in Spring of 2018 as a proof of concept Black Mesa Labs project on being able to design and assemble a 1mm pitch BGA using only a 4-layer PCB from OSH Park. Xilinx manufactured their last TQFP with ISE Specific Spartan6, so moving to Vivado and Spartan7 required a BGA design and assembly solution for Black Mesa Labs to continue. Details of the original prototype can be read on my S7-Mini Google Docs presentation .  The prototype was 100% successful aside from mass producing, so Black Mesa Labs contacted Trenz Electronic in Germany who agreed to make improvements for manufacturability and assemble, test and sell S7 Mini boards from their website. By the Fall of 2018 Trenz had working prototypes delivered to BML for evaluation. In Spring of 2019 the S7 Mini became a Trenz product for about $40 and is recognized by Xilinx on their website.

s7_mini_xilinx_website

[ Plug In Boards ]

Black Mesa Labs has two 50mil ( 1.27mm ) plug in board designs for the S7 Mini that provide either 4 or 8 standard Digilent Inc PMOD connectors. Each PMOD provides 8 LVCMOS I/Os. The octa-pmod may be ordered from OSH Park here. The quad-PMOD may be ordered from OSH Park here.  TODO: In the future both designs will be on GitHub along with Gerbers, BOM and assembly instructions.

GitHub octa-pmod design link is here.

octapmod_to_4dvi

Here is a Twitter Link to a video of the Octa-PMOD board driving multiple HDMI/DVI monitors using the BML PMOD-to-DVI board that is now produced by 1bitsquared as part of the Ice Breaker crowd funded Lattice FPGA board.  Hopefully in the future the PMOD to DVI boards will also be sold separately. Will Green ( @WillFlux ) has some excellent tutorials on interfacing with these PMOD to DVI modules here. BML’s latest is PMOD to DVI provides full 24bit color using DDR and is available here.

[ GitHub example designs for the S7 Mini ]

bml_s7_mini_github

  1. Hello World blinky LED design.
  2. PMOD template designs.
  3. Making DVI video using PMOD to DVI boards.
  4. MesaBus virtual 32bit PCI link over FTDI cable using bd_shell.py.
  5. Bootloader design for updating PROM firmware using bd_shell.py + FTDI cable.
  6. HyperRAM example design.
  7. SUMP2 Logic Analyzer using sump2.py GUI on PyGame.
  8. SUMP2+DeepSump Logic Analyzer using bd_shell.py and GTKwave.

EOF

BML S7-Mini FPGA Module

4 thoughts on “BML S7-Mini FPGA Module

  1. RodRico says:

    Your design rocks! I’m through the preliminary design of a Forth CPU for Spartan 7, and have decided to target your board rather than Digilent’s CMOD S7. Going into place and route, it looks like I’ll be able to run 125 million Forth primitives per second with average clock margin of 45% and minimum clock margin of 19% (Block RAM to Stacks during memory read). The design is single cycle with fixed 8ns instruction and interrupt latency time, so it’s pretty handy for embedded control, and it uses few resources (under 500 LUT, 1 DSP Slice, and 16 x 36kb Block RAMs for 64KB user memory). Folks can use your PMOD expanders to add DVI, USB, SD Cards, etc., but I plan to provide a very basic development environment using the configuration memory for 6.8 MB file storage combined with monochrome 800×600 VGA with PS/2 keyboard and mouse via a simple cable dongle off the base board. Thanks for making this beauty!

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