BML USB 3.0 FPGA interface over PMOD

2017.12.19 :  Black Mesa Labs is presenting an open-source-hardware USB 3.0 to FPGA PMOD interface design.  First off, please lower your expectations. USB 3.0 physical layer is capable of 5 Gbps, or 640 MBytes/Sec. This project can’t provide that to your FPGA over 2 PMOD connectors – not even close. It does substantially improve PC to FPGA bandwidth however, 30x for Writes and 100x for Reads compared to a standard FTDI cable based on the FT232 ( ala RS232 like UART interface at 921,600 baud ). A standard FTDI cable is $20 and the FT600 chip is less than $10, so BML deemed it a project worth pursuing.

IMG_2548.JPG

Measured Data Transfers comparing FT600 to FT232:

USB 3.0 to FT600 at 100 MHz: Writes=1,384 KBytes/Sec, Reads=567 KBytes/Sec

USB 3.0 to HUB to FT600 at 100 MHz: Writes=416 KBytes/Sec, Reads=187 KBytes/Sec

USB 2.0 to FT600 at 100 MHz: Writes=279 KBytes/Sec, Reads=131 KBytes/Sec

USB 2.0 to FT232 1×6 0.100″ at 1 Mbps: Writes=43 KBytes/Sec, Reads=5 KBytes/Sec

Wait, what?  Measured in KBytes not MBytes per second? Is BML to blame? Only partly. This BML project utilizes 1/4 of the LVCMOS bandwidth possible of the FT600 to both make the IO fit across PMODs and also work with existing Mesa Bus Protocol IP.  The FT600 has 16 data pins capable of 200 MBytes/Sec but 1/2 the data pins are deliberately tossed to fit within 2 PMODs ( 3 PMODs wouldn’t be practical ).  Existing Mesa Bus Protocol IP is used – which transfers ASCII nibbles (0-9,A-F) instead of binary, so the maximum logical throughput is reduced another 2x to 50 MBytes/Sec.  Observed transfers are just over 1 MByte/Sec.  This means if all 16 pins were used and a binary protocol transfer instead of ASCII, rate would be about 5MBytes/Sec – still away off from 200 MB/s . So what is going on? This is a perfect application for the SUMP2 Logic Analyzer from BML.  Instead of wiring up the iceStick, SUMP2 was instantiated directly in the FPGA along with the FT600 interface ( this is really what SUMP2 is designed for, a free open-source replacement for Xilinx ChipScope and Altera SignalTap. SUMP2 supports capturing 32 compressed events and up to 16 non-compressed DWORDs into on-chip FPGA block RAM ). Below is a PNG screen dump of SUMP2 capturing the FT600 FIFO status flags (RXF,TXE) and the FPGAs control signals ( RD,WR ). What is immediately apparent is that the majority of the time ( ~154uS out of ~160uS ) the FT600 doesn’t have any data for the FPGA. RXF is sitting low even though Python is trying to send data as fast as possible.

sump2_0009.png

Within a 10 ns clock cycle of RXF asserting, the FPGA asserts RD and converts the Mesa Bus Packet into a local bus burst ( with about 350ns of pipeline latency ). The observed distance between the 32bit lb_wr pulses is precisely 8 clocks, the fastest possible ( DWORD = 4 Bytes x 2 ASCII Bytes per Binary Byte = 8 clocks ).  Clearly both the FT600 and the FPGA design are working as fast as possible with what is coming down the USB 3 pipe.sump2_0010.png

So, the truth is that the majority of the time ( 154/160us = 96% ) the PMOD interface is sitting idle even though Python is trying to write and read from the FT600 as fast as it can. Clearly the USB 3.0 pipe is not full. Who is to blame? Is it Python? Windows? Intel Chipset? Don’t know. Would it be faster on Linux? Hopefully. Would compiled C be faster than Python? Probably. Would we ever achieve 50 MBytes/Sec? Probably not. FTDI Application Note AN_386 goes into some detail, there is a lot of software between the user software and when the electrons finally hit the USB 3.0 cable.

Is just over 1MBytes/Sec a disappointment? Yes.  A show stopper? No. Using the FT600 is still the fastest way (BML is aware) of inexpensively getting data from a PC into any FPGA without instantiating a PCI Express IP core and building a PCI Expresss plug in card. 30x and 100x improvements on Writes and Reads is substantial.

2017.12.20 – Update, an acquaintance on Twitter has reported using an FT600 with a proper C client over an FMC connector (all 16 pins, 100 MHz,  binary transfers ) of 185 MB/s ( out of 200 MB/s total ). That is excellent news and proof that Python is most likely the bottleneck. Based on his results, the BML dual-PMOD board should be capable of 1/4 that ( 8bit, ASCII ) or 46 MB/s. Github link to C source is here.

2017.12.21 – Update – another acquaintance on Twitter has reported achieving 240 MB/s using FT601 ( 32bit ) and C on Linux. His USB interface software is on Github here.

Now that performance explained – About the design, let’s begin:

[ Software Setup ]

Step-1) Download and install FTD3XX Device Driver from FTDIchip.com .  For example, for Windows, download and run FTD3XXDriver_WHQLCertified_v1.2.0.6_Installer.exe

Step-2) Download and install Python module for D3XX from FTDIchip.com.  For example, unzip D3XXPython_Release1.0.zip, “%cd D3XXPython_Release1.0” and then “%python setup.py install”

Step-3) Create a directory for your script and copy FTD3XX.dll and FTD3XX.lib from unzipped D3XXPython_Release1.0 folder.

[ Hardware Setup ]

Board design.  The board is a 2-layer PCB that is available either via Gerber download or direct purchase from OSH-Park here ($10 for Qty-3). The board consists of the FT600 chip from FTDI, 3 LDO regulators, a 30 MHz crystal and a bunch of 0603 and 0805 passives ( 10uF, 0.1uF, 18pF, 10K, 1.6K, 33 ohm, Ferrite Bead ).

bml_ftdi_usb3_to_pmod

FPGA Hardware setup is a bunch of Verilog IP.  I/O timing over the PMODs was tight, so a PLL is used to remove clock tree insertion delay on the 66/100 MHz clock provided by the FT600. Xilinx Spartan3 LVCMOS 3.3V 8mA Fast IO buffers were required to run at 100 MHz. Since actual throughput doesn’t really get impacted, it is recommended to run at 66 MHz unless a 100 MHz clock is needed for other reasons. The clock from the FT600 is software selectable to be either 66 MHz or 100 MHz and the clock automatically shuts off when USB sleeps during inactivity. Thankfully, it turns on 100’s of ms prior to data transfers, allowing for PLLs to lock if needed.  WARNING: An annoying feature of the FT600 is that using the FTDI configuration program you can select to keep the FT600 clock on always – but what isn’t mentioned is that if you select this option, the device will no longer work with USB 2.0 – at all.

File_000 (12)_cropped.jpeg

Design files are here on my public dropbox. They include example Python for testing Write/Read performance, Bill of Materials, Gerbers, Layout files, Layout Screen Shots and example Verilog test design working on a Xilinx Spartan3. A future blog post will go into details on using Mesa Bus Protocol for virtual 32bit PCI like register reads and writes both from user Python and with bd_shell.exe – a Windows .NET app written in Powershell that provides a useful command line interface for writing, reading and scripting register access over a Mesa Bus Protocol link ( either FT600 dual-PMOD or simple FT232 2-wire. A new version of bd_server.py here supports both FT232 and FT600 interfaces for applications like sump2.py and bd_shell.exe to share access to FPGA memory space using Mesa Bus Protocol over Berkeley Sockets for ICP. SUMP2 works great over the FT600, especially for captures with 16 DWORDs of data at 8K samples – the 100x faster reads makes a huge difference.

Stay tuned for more BML open-source hardware and software projects that utilize this FT600 USB 3.0 interface.  Follow me on twitter @bml_khubbard

[EOF]

 

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BML USB 3.0 FPGA interface over PMOD

BML DVI digital video for FPGAs over PMOD

IMG_2528

2017.12.15 :  Black Mesa Labs is proud to present two open-source-hardware DVI  video boards for adding TMDS digital video to FPGA platforms with standard PMOD connectors.  These two boards are currently available to purchase as bare fabs directly from OSH-Park, or Gerbers and design files may be downloaded from BML here.

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BML 3bit DVI over single-PMOD:

bml_3b_hdmi_top_and_bottom.PNG

The BML 3bit DVI over single-PMOD uses 7 of 8 available LVCMOS 3.3 pins on a single PMOD to provide 3bit color ( R,G,B 100% On or Off ). Example Verilog design drives 800×600 using a 40 MHz dot clock. The TI TFP410 is very versatile in the resolutions it can generate and is really just limited by the clock that the FPGA can provide and the data rates the PMOD connectors are capable of. The bare 2-layer fab may be purchased from OSH-Park directly for $5 USD ( for 3 boards ) from this link. The TFP410 is about $8 USD. The IC and this HDMI Connector is pretty much the BOM, so the entire cost to assemble is less than $20 USD. The rest of the BOM is Qty-2 0603 0.1uF Caps ( 25V 20% X7Rs were used ), Qty-1 0603 10uF Cap, Qty-1 0805 500ohm 1% resistor and an optional 0805 Ferrite Bead ( 240-2390-1-ND was used, but may be replaced with a wire ).  If you don’t want to power the TFP410 from your FPGA’s 3V rail, the Ferrite Bead may be removed and a BU33 ( or equivalent 5SSOP) 3.3V LDO regulator and 10uF cap may be stuffed and the board may be powered by a 5V input via.

The 3bit color Test Pattern from the board driven by FPGA sample design looks like this:IMG_2530.JPG

Note that blue exists, it is just off screen.  With 3bits of color you get 8 colors by additive color mixing  for Black, White, Red, Green, Blue,  Yellow, Cyan, Magenta.

Below is a picture of the 3b board plugged into a Lattice ICE40 icoBoard which is available from Trenz here.  The smaller iceZero board (PiZero dimensions), also a Lattice ICE40 is a joint BML and Trenz design and would also be a good platform for DVI video and is available here.

IMG_2539.JPG

Design files for the board, including Gerbers, BOM and text netlist description may be downloaded from my public Dropbox here.

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BML 12bit DVI over dual-PMOD:
bml_12b_hdmi_top_and_bottom.PNG

The BML 12bit DVI over dual-PMOD uses 16 of 16 available LVCMOS 3.3 pins on two PMODs spaced 0.900″ center-to-center per Digilent spec. The 12bit color provides 16 shades each for Red, Green and Blue. Example Verilog design drives 800×600 using a 40 MHz dot clock.  The bare 2-layer fab may be purchased from OSH-Park directly for $11 USD ( for 3 boards ) from this link. BOM is identical to the 3b version, just another PMOD 2×6 right-angle 0.100″ female connector is added. Test Pattern video from the board looks like this ( blue is off screen ):

IMG_2531.JPG

Example Verilog.  The open-source example Verilog here was used to generate the test patterns shown from a Xilinx Spartan3 board. The design itself is very portable and only requires the FPGA to have a 40 MHz clock and the ability to mirror the clock out to the TFP410 IC using a ODDR or equivalent DDR clock mirroring and the IO ring.  If IO timing for your particular FPGA board doesn’t work, often it may be tweaked to work by adjusting the drive strength and slew rates of the clock out relative to the data out.  Note: BML deliberately chose NOT to use the built-in DDR capability of the TFP410 due to wide variability of I/O timing from various FPGA boards over PMOD interfaces.  SDR is most likely to work across platforms so it was chosen.

A word about video timing – it is tricky. The TFP410 will generate just about any timing you throw at it, but your monitor ( or TV ) might not like it. This on-line calculator is extremely helpful in calculating all the Sync Widths, Front Porch, Back Porch timing parameters. Provided with a resolution ( 800×600 for example ) it will spit out the Verilog def_h_total and def_v_total times ( 1000×667 at 40 MHz for 60 Hz for example ) and the blanking times ( Hsync and Vsync widths, 56 and 3 for example for def_h_sync, def_v_sync ). The porch numbers are then whatever is left over. For example 1000-800-56 = 144. 144/2 = 72 which should work for def_h_fp ( Front Porch ) and def_h_bp ( Back Porch ). It takes patience and experimentation to generate something your monitor is happy with. If your display locks, but isn’t centered, then your porch numbers need to be adjusted accordingly.

IMG_2535.JPG

BML hopes that you enjoy these free and open-source board designs for adding DVI video to FPGAs. Check back soon for posting on new USB 3.0 to PMOD adapter using FTDI FT600 FIFO Chip.

2017.12.19 : Updated to fix Gerbers for 3b version with incorrect soldermask on video connector.

[EOF]

BML DVI digital video for FPGAs over PMOD

BML 50mil (0.050″ , 1.27mm) Proto Boards for Rapid Surface Mount Prototyping

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2017.12.03

0.100″ proto boards are readily available and great for prototyping with 1980’s DIP thru-hole technology.  Trying to use them with 1990s and newer surface mount devices is like picking your teeth with a log however.  0.050″ pitch vias line up perfectly with SOIC ICs, SOT-23s and 0603s passives but for whatever reason proto boards with 0.050″ pitch don’t really exist.  Black Mesa Labs aims to change that. BML is proud to introduce a family of 0.050″ pitch proto boards for interfacing with Arduino, RaspPi and FPGA boards. All boards designs are available for free and may be purchased from OSH-Park directly or optionally downloaded as Gerbers and CopperConnection layout files from my public Dropbox here.  If you don’t want the convenience ( and free shipping ) of ordering directly from OSH-Park, the Gerbers may be uploaded to most PCB fabs ( for example, ITEAD in China ).

P.S. – While you air wire your circuit together, don’t forget to use some Copper tape to add extra ground returns and signal shields.

IMG_2513

These FPGA single PMOD boards come in 1″, 2″ and 3″ lengths ( 2.5cm, 5cm, 7.5cm ). They provide both a GND and 3.3V perimeter. They have a FPGA PMOD connector footprint on the left, but may be used standalone of course without an FPGA board.

Click here to purchase Qty-3 of these 3″ PCBs for $10 from OSH-Park.

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Click here to purchase Qty-3 of these 2″ PCBs for $7 from OSH-Park.

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Click here to purchase Qty-3 of these 1″ PCBs for $4 from OSH-Park.

bml_pmod_to_050_grid_1_inch.png

 

These FPGA dual-PMOD boards also come in 1″, 2″ and 3″ lengths ( 2.5cm, 5cm, 7.5cm ). They provide both a GND and 3.3V perimeter.

IMG_2512.JPG

Click here to purchase Qty-3 of these 3″ PCBs for $24 from OSH-Park.

bml_dual_pmod_to_050_grid_3_inch.png

Click here to purchase Qty-3 of these 2″ PCBs for $16 from OSH-Park.

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Click here to purchase Qty-3 of these 1″ PCBs for $8 from OSH-Park.

bml_dual_pmod_to_050_grid_1_inch.png

The Arduino UNO board should mate with any board with a UNO footprint. It has a GND, 3V and 5V perimeter ring around the 0.050″ grid. There is also a 2×15 0.100″ grid on the left for external interfacing ( or large components ).  A FTDI 1×6 0.100″ connector is available for (optionally) connecting to the Arduino RX and TX serial lines.

IMG_2549.JPG

Click here to purchase Qty-3 of these for $22 from OSH-Park.

bml_arduino_uno__050_grid_shield.png

The Arduino ProMini shield is extremely multipurpose as it can be used to interface small SMT devices on a 0.050″ grid to a standard DIP 0.600″ grid ( breadboards ). PCB design uses castellated 0.100″ vias on the perimeter allowing this board to be soldered directly to the back of a Pro-Mini or any 0.100″ proto board without requiring any tall headers. Kapton tape should be placed between PCBs to prevent shorting. If you have just a few surface mount components you want to add to a bigger 0.100″ proto board design – this is the board for you. Cheap too.

Click here to purchase Qty-3 of these for $4 from OSH-Park.

If you don’t already know about the Arduino Pro-Mini – it’s an awesome deal for $10.

bml_arduino_promini_050_grid_shield.png

The Pi Zero shield may be used with any Pi with a 2×20 0.100″ header. It has a GND, 5V and 3V perimeter ring around the 0.050″ grid.  2×7 0.100″ grids are available on both the left and right sides of the board.

Click here to purchase Qty-3 of these for $15 from OSH-Park.

bml_pi_zero_050_proto.png

And finally, BML is working on a family of SMT to 0.050″ “sleds”. Castellated PCBs for breaking out really small SMT stuff to the larger 0.050″ grid.

IMG_2515.JPG

 

Misc SOIC-16 to 0.050″ castellated for like $1.

Misc SOIC-8 / SOT-23-8 to 0.050″ castellated for like $1.

Misc TSSOP-28 to 0.050″ castellated for like $1.

Misc QFN32 to 0.050″ castellated for like $1. ( Example ADV7280 package )

Looking for something else? Let me know – we can most likely work something out.

 

 

 

BML 50mil (0.050″ , 1.27mm) Proto Boards for Rapid Surface Mount Prototyping

IceZero FPGA Hat for RaspberryPi Servo Example

2017.07.04 :  Black Mesa Labs has some exciting news, the open-source IceZero FPGA Hat for RaspberryPi designed in December in 2016 ( and free to download Gerbers ) has been picked up by Trenz Electronics as a fully assembled product ready to ship and plug into a RaspberryPi. The Lattice FPGA is fully compatible with Clifford Wolf’s open-source icoTC tool chain for Verilog synthesis to FPGA bitstream.

TE0876-01_0.jpg

This post provides an example design for expanding any RaspberryPi to have 32 GPIO pins and 6 PWM ( Pulse Width Modulators ) for driving Servos, LEDs, reading switches, etc. The best part is that NO FPGA design experience is required.  The simplest way to get up and running is to download the FPGA bitstream file, load it into the PROM using provided programming tool and then start your project with the example Python for configuring the 32 GPIO pins available on the IceZero ( 4 2×6 PMOD connectors ).

File_000 (6).jpeg

 

Step-1) Download either the Entire Big Design, or just the Bitstream and Python files.

Step-2) Plug the IceZero onto the RaspberryPi and use included python script to program bitstream into PROM.

%python ice_zero_prog.py gpio32_pwm6_te.bin

Note that the Bulk erasing procedure takes about a minute. Note, Clifford Wolf has written icezprog.c a C based PROM programmer for the IceZero that may be considerably faster. Worth checking out.

prog_example.png

Step-3) If all is well, the 3 LEDs on the IceZero will be flashing again in a binary 3bit counter fashion.  Now you can look at the example servo_te.py example for configuring the 32 GPIO pins and the 6 PWM controllers.  The example design listens to 6 pushbuttons ( Increase, Stop, Decrease ) that are used for controlling 2 PWM blocks for 2 servos on a Pan/Tilt kit for a RaspberryPi camera.

Details regarding GPIO design – the reg_space.txt file is a detailed register description on controlling the 32 pins.  The IceZero has 4 PMOD connectors P1,P2,P3,P4 and there are corresponding registers for controlling them. For example:  The register PMOD_P1_CFG controls the pin configuration (CFG) for P1.  The 8 pins on P1 may be individually configured as input, output or PWM controlled.  PMOD_p1_CTRL then is used for reading status of P1 inputs and controlling P1 outputs.

Check back later for more details to be filled in.

 

IceZero FPGA Hat for RaspberryPi Servo Example

IceZero FPGA Board for RaspPi

ice_zero_with_pi_zero.jpeg

2017.02.07 : BML has been very much enchanted with the Lattice FPGA boards for Raspberry Pi, IcoBoard , BlackIce and IceHat. The IceZero board is a BML creation that attempts to combine the best features of all 3 boards into a single design. Hackaday article here.

[ IceZero Block Diagram ]

bml_icezero_block_diagram.png

[ IceZero features common with other designs ]

  1. Fully Open-Source Hardware and Software Design.
  2. Lattice ICE40HX4K FPGA that supports Clifford Wolf’s Project IceStorm tool chain.
  3. Interfaces to Raspberry Pi 2×20 GPIO Header for both power and bus interfaces.
  4. PROM programmable directly from Rasp Pi, no JTAG programmer required.
  5. External SRAM, supporting soft CPU core designs ( code execution ).
  6. Extra large SPI PROM, supporting soft CPU core designs ( code storage ).
  7. Industry standard PMOD expansion headers

[ IceZero features that are BML specific ]

  1. Mesa Bus Protocol 32 MHz SPI link between CPU and FPGA.
  2. 2-Layer PCB design. Orderable via OSH-Park or Gerbers for Downloading.
  3. FTDI 1×6 USB Serial Cable header for use with PC instead of Pi ( or as a soft CPU debug Trace Port ).
  4. Single Pi UART plumbed to FPGA for muxing to multiple external serial devices.

[ Board Design ]:

Please see the IceZero Hardware Design Document and check back for updates.

kevins_art.png

IceZero is drawn as a 2-layer PCB using CopperConnection from RobotRoom, an excellent PCB drawing tool. Board dimension are 2.57×1.18 inches (65.20×30.02mm) , or the near equivalent outline of a Raspberry Pi Zero.

Top:

Top side contains FPGA, SPI PROM, 3 LDOs ( 3.3V, 3.3V, 1.2V ) a OK LED, misc passives and optional 0.100″ PMOD connectors ( 2×6 and 1×6 ) and a single 1×6 0.100″ FTDI header.

bml_ice_zero_front.png

Bottom:

Bottom side contains 100 MHz MEMs oscillator, 256Kx16 SRAM and misc passives.

bml_ice_zero_back.png

[ Bill of Materials ]

Qty-1 : 220-1572-ND : ICE40HX4K-TQ144 : IC FPGA 107 I/O 144TQFP : $5.77
Qty-1 : 706-1306-1-ND : IS61LV25616AL-10TL-TR : IC SRAM 4MBIT 10NS 44TSOP : $3.36
Qty-1 : 1473-1484-1-ND : SIT8008BI-12-XXE-100.000000G : OSC MEMS 100.0000MHZ LVCMOS SMD : $1.23
Qty-1 : 557-1562-ND : N25Q128A13ESE40E : IC FLASH 128MBIT 108MHZ 8SO : $1.82
Qty-2 : BU33TD3WGCT-ND : BU33TD3WG-TR : IC REG LDO 3.3V 0.2A 5SSOP : $0.28
Qty-1 : BU12TD3WGCT-ND : BU12TD3WG-TR : IC REG LDO 1.2V 0.2A 5SSOP : $0.28
Qty-10 : 1276-5086-1-ND : RC1608J103CS : RES SMD 10K OHM 5% 1/10W 0603 : $0.01
Qty-1 : 1276-5062-1-ND : RC1608J102CS : RES SMD 1K OHM 5% 1/10W 0603 : $0.01
Qty-4 : 1276-2087-1-ND : CL10B475KQ8NQNC : CAP CER 4.7UF 6.3V X7R 0603 : $0.03
Qty-16 : 490-9730-1-ND : GRM188R70J104KA01D : CAP CER 0.1UF 6.3V X7R 0603 : $0.03
Qty-1 : 641-1332-1-ND : CDBU0520 : DIODE SCHOTTKY 20V 500MA 0603 : $0.22
Qty-1 : 160-1176-1-ND : LTST-C170CKT : LED RED CLEAR 0805 SMD : $0.15

Optional:
Qty-1 : 2×20 0.100″ Straight Female Connector ( PI GPIO )
Qty-2 : 2×6 0.100″ Straight or Right Angle Female Connector (PMOD)
Qty-2 : 1×6 0.100″ Straight or Right Angle Female Connector (PMOD)
Qty-1 : 1×6 0.100″ Straight or Right Angle Male Connector (FTDI)

WARNING : The Micron 128Mb SPI PROM is end-of-lifing from DigiKey, so future builds will use a different PROM. Considering switching to Micron 64Mb N25Q064A13ESE40F or Cypress 64Mb S25FL164K0XMFI010 for cost and availability reasons. FPGA itself only requires 1Mb, everything above that is useful for soft CPU development for code storage. 64Mb at $0.85 is nice compromise.

[ Ordering IceZero ]

badge-5b7ec47045b78aef6eb9d83b3bac6b1920de805e9a0c227658eac6e19a045b9c.png

bml_ice_zero_osh_park.png

Right now, ordering bare PCB fabs is the only method for getting an IceZero board. Click on this link for ordering Qty-3 PCBs for $15  from OSH-Park. If there is interest, I will send Gerbers out for fab in China and could PayPal sell and ship single bare PCBs within the U.S. for maybe $5 – TBD. You may also optionally download the OSH Gerbers or CopperConnection layout files. All files are provided complete AS-IS and are provided under the CERN Open Hardware Licence.

[ IceZero License Statement ]

This project is licensed with the CERN Open Hardware Licence v1.2. You may redistribute and modify this project under the terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
This project is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.2 for applicable Conditions.

[ FPGA Programming ]

The Python script ice_zero_prog.py may be used for downloading a Lattice PROM file into the SPI PROM from a Raspberry Pi.  This PROM utility is available on GitHub.

[ SUMP2 Sample Design ]

A SUMP2 Verilog sample design for the IceZero is available on my Dropbox. This uses the same Pi software as SUMP2 for IcoBoard.  A very important feature of the IceZero sample design is that it may be used with zero FPGA experience as both a Logic Analyzer and a generic GPIO port expander, providing 24 software defined pins for things like reading switching, driving LEDs and even PWM outputs for servo control.
sump2_on_ice_zero.jpeg

[EOF]

IceZero FPGA Board for RaspPi

SUMP2 100 MSPS 32bit Logic Analyzer for icoBoard+RaspberryPi

2016.12.22 : After publishing SUMP2 96 MSPS Logic Analyzer for $22 iCEstick, BML was contacted by the icoBoard team in Austria inquiring the feasibility of running SUMP2 on their Lattice FPGA on the icoBoard and the RaspberryPi. BML was up for the challenge and has successfully ported the Windows + iceStick SUMP2 to work on Linux on Pi + icoBoard. This post describes how to configure the RaspberryPi and icoBoard to be a standalone 32 channel 100 MSPS logic analyzer.

File Download Area ( BML’s Dropbox ):

Note: See BML’s GitHub also https://github.com/blackmesalabs

What is needed:

  1. A Raspberry Pi Model3 ( or faster ), a USB mouse and a HDMI display.
  2. An icoBoard from icoboard.org.
  3. Free open-source software and firmware for SUMP2 from Black Mesa Labs.

Step-1 ) Download the 2GB custom Jessie-Lite image. Full details on this image ( and how to recreate from scratch if desired ) are available here. This image is a console only Linux that has Python modules pre-installed and a boot mechanism for installing files from a AppData.tgz file on a USB stick. Users may choose to manually install contents of AppData.tgz on their existing Linux Pi images, but no support for this is offered by BML.

Step-2) Burn the 2GB image to a uSD card using Win32DiskImager or similar tool. Warning – if you use a 2GB card, it might not work if it has fewer sectors than the 2GB card used in the generation of the image. Recommend using a 4GB uSD just to be safe.

Step-3 ) Boot the Pi with the new card.  It should boot up to a “Hello World” message.

Step-4) Download and Copy AppData.tgz and install_software.txt files from BML to a USB flash drive’s root directory.

Step-5) Boot the Pi with the USB flash drive. It should now install and launch the SUMP2 GUI.

Step-6) Configure the FPGA PROM by right-clicking in the waveform area of the screen ( not the signal name area ) and select System, Load_FPGA.  After this has completed, right click again and select System,Reboot. Remove the USB stick to prevent software from re-installing on the next boot.

Step-7) After the reboot the SUMP2 firmware and software should be fully functional.

sump2_0000.jpg

[ About the design ]

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SUMP2 is entirely open-source hardware ( Verilog RTL FPGA design ) and open-source software ( Python GUI ).   The open-source Hardware and Software design files for the icoBoard version are all available here.  Please read the original SUMP2 for iCEstick blog for more detailed information on SUMP2. The icoBoard version uses a Lattice iCE40HX8K which roughly has 8x the FPGA fabric resources as the iCE401K on the iCEstick. Instead of using asynchronous 1 MHz serial communication ( FTDI 921,600 baud over USB ), the icoBoard uses the Raspberry Pi’s built in SPI interface running at 32 MHz. Both versions of SUMP2 use Mesa Bus Protocol for transferring 32bit virtual PCI write and read cycles over serial interfaces. SUMP2.py for icoBoard communicates directly with the hardware, unlike SUMP2.py for used TCP sockets for communication to bd_server.py as a hardware/software abstraction layer. Setup for SUMP2 on icoBoard is much easier as the open-source nature of the Pi platform allows BML to design for a walled garden environment ( made completely of open-source mind you ). BML provides the OS and the Application and the user provides the hardware of which there is a single choice, icoBoard and a Pi Model 3. Only variable to test for is differing HDMI screen resolutions.

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[ PMOD Pinouts ]

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The icoBoard has 4 0.100″ 2×6 PMOD connectors labeled P1-P4. Each connector is 1 of 4 byte inputs to SUMP2 for LVCMOS 3.3V signals.  P1 corresponds to events[7:0], P2 events[15:8], P3 events[23:16], P4 events[31:24].

[ SUMP2 on a small HDMI Display ]

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Large LCDs are fantastic, but if you want a small footprint dedicated logic analyzer to sit next to your bench scope, SUMP2 can do that too. With the exception of optional signal renaming, the SUMP2 software interface is entirely mouse driven, no bulky keyboard required to operate. No Linux login required. SUMP2 boots and runs like an oscilloscope – OS is completely in the background, hidden from the end user ( but absolutely still available to them for tinkering ). The final BML setup for SUMP2 on icoBoard uses a small 7″ 800×480 LCD and the Pi+icoBoard easily attaches in the rear with some doubled sided velcro tape. Although the standard Linux text console (shown above) is much too small to read at 800×480 on 7″, the SUMP2 menu option Misc,Font_Larger or Font_Smaller allows for changing font size on the fly to make for a compact and readable display (shown below).  Note that this setup uses the -bundle option in the sump2_wave.txt file to group multiple signals into a single “bus” that is then displayed as hexadecimal instead of a binary waveform. More details are available in the file sump2_manual-txt.

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[ Executing from USB Flash Drive ]

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BML opted to execute the SUMP2 software from an external USB stick instead of the on board Pi uSD card. To accomplish this, simply copy the folder ~/AppData to /media/usb0 ( or do this from a PC ).  The advantage of running SUMP2 from USB is that transferring screen captures ( PNG, JPEGs ) and VCD exports from SUMP2 from the Pi to a PC much easier. If running SUMP2 with only a mouse ( no keyboard ), signal renaming is still possible by removing the USB stick with the Pi off and manually editing the ./AppData/sump2_wave.txt file using Vi or similar editor prior to booting the Pi. Configuration of the GUI is all clear text within sump2.ini and sump2_wave.txt files.

[ Flying lead adapter to PMOD ]
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For just $1, this PCB may be ordered from OSH-Park that labels and adapts a PMOD connector to signal and ground pair 0.050″ pitch vias for making a flying lead adapter with dedicated signal ground returns for optimal signal integrity.

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A slightly different version available here instead breaks out the PMOD to a 1×8 0.100″ row along with a single GND pin and 3V pin suitable for slow signals and dupont cables.

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This PMOD2PMOD board allows 2 PMODs Masters to plug into each other, for example 2 icoBoards can interact with 2 of these for 16 IOs between them. Useful for using SUMP2 on one icoBoard for debugging another FPGA design. 3V are not connected, only signals and grounds. Note that the signals are twisted 0->7, 1->6, etc and should be untwisted in the FPGA fabric.

 

[ Making PMOD inputs 5V Tolerant ]

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The PMOD inputs of the icoBoard are 3V only and are NOT 5V tolerant. Since both the iCEstick and icoBoard use the same PMOD connectors, the 5V tolerant input adapter designed by BML for the original SUMP2 on iCEstick may also be used on the icoBoard. The bare PCBs may be ordered at this link direct from OSH-Park for $5.  With the bare PCB, a simple 2×6 0.100″ right angle male header and a DIP SN74LVC244AN may then be soldered to provide a 3V input to icoBoard that is also 5V tolerant.  Total cost of parts and PCBs for 3 PMOD connectors total is only about $10. WARNING: Care must be taken not to configure the FPGA GPIO features as outputs to prevent damaging the FPGA. By default, the FPGA powers up with PMOD pins configured as inputs, allowing safe operation with this adapter.

[ GPIO Feature ]

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But wait, there is more.  The Lattice iCE40HX8K FPGA on the icoBoard has 8x the resources of the iCEstick, so along with the SUMP2 logic analyzer engine, the FPGA design also includes 8 PWM ( pulse width modulators ) and GPIO ( General Purpose Input Output ) capabilities for all 32 PMOD signals.  Completely unrelated to SUMP2, this feature bundled in the same FPGA bitstream may be used as a general purpose port expander for the Raspberry Pi.  With time-multiplexing, the design actually supports controlling 32 RC servos ( only 8 in motion at once ).  By default, the GPIO portion of the FPGA design powers up with a 32 PMOD signals as inputs, allowing SUMP2 to operate on external signals without programming the GPIO registers. Refer to the ./source/reg_space.txt file for detailed register descriptions on programming the GPIO module. The example file ico_gpio.py included in AppData.tgz demonstrates how Python and Mesa Bus Protocol can be used for configuring the GPIO features. Conversely, the SUMP2 FPGA bitstream may be used without ever using SUMP2 if a Pi user simply wants to add more IO capabilities to their Pi.  Look for future GPIO FPGA only design from BML for the iCEstick that may be used for bit-banging any 3V device from a PC using Python ( including writing and reading SPI and I^2 PROMs ). $22 makes for a very nice platform for controlling devices and monitoring switches from any PC with a USB port.

[ Built in Self Test (BIST) Feature ]

The GPIO feature of the FPGA design and the included ico_gpio.py software may be used to drive test stimulus to all 32 PMOD pins.  This feature is useful for testing that all the SUMP2 software and hardware is operational. The electronic stimulus is provided by the SPI interface between the FPGA and Pi and the 8 PWM units.  WARNING : Enabling this feature drives the test data as FPGA outputs to the PMOD connectors, so it is important that nothing be connected to them ( including the 5V to 3V translation boards ). Running ico_gpio.py which enables all the output buffers of the FPGA may damage the FPGA if other devices are also driving the PMOD pins. Only run ico_gpio.py if you are certain nothing is electrically connected to the PMOD pins.

Step-1 ) From SUMP2 GUI, select System, Quit.

Step-2 ) From Linux command line, type %python ico_gpio.py   ( Configs GPIO outputs )

Step-3 ) From Linux command line, type %source start_app.sh   ( relaunches GUI )

[ Demo at 33C3 ]

Clifford of icoBoard.org demonstrated SUMP2 running at the 2016 Chaos Communication Congress (33C3) festival in Hamburg Germany.

A post shared by Clifford Wolf (@cliffordvienna) on

 

[ In Closing ]

Please enjoy SUMP2, a 32 channel 100 MSPS open-source logic analyzer for icoBoard and RaspberryPi.  Follow BML on Twitter for updates on SUMP2 and other open-source software and hardware projects from Black Mesa Labs.

EOF

SUMP2 100 MSPS 32bit Logic Analyzer for icoBoard+RaspberryPi

SUMP2 – 96 MSPS Logic Analyzer for $22

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2016.22.22 : SUMP2 now also available for RaspPi+icoBoard here.

2016.12.13 : Great video on SUMP2 from Bil Herd at Hackaday.

2016.10.31: Thanx to SteveDC, a 3D printed case is now available for SUMP2 here.

2016.10.30 : SUMP2 5V Input shield is now available from OSH-Park for $5. BML can also design similar shields for RS232,RS422/485,LVDS and CAN Bus if there is any interest.

2016.10.24 : Black Mesa Labs has an ongoing mission to develop easy to use and fully capable open-source hardware and software tools that make engineering electronics easier. One such tool is this new low cost open-source logic analyzer called SUMP2 for people who otherwise work in the blind without an oscilloscope or logic analyzer on their bench top.  BML’s 1st incarnation called SUMP1-RLE in 2014 was a 16bit FPGA based logic analyzer that performed real-time hardware compression and decompression. The decompressed data was streamed out over USB using the open SUMP protocol ( hence the name ), allowing it to be used with the excellent Java software from the original 2007 sump.org project. The SUMP1-RLE project was later enhanced from just 16 triggerable events to also include 2 DWORDs of “data” ( additional 64bits of non-triggering non-compressed signals ) and advanced triggering options. Including the data DWORDs made SUMP1 a useful tool for complex FPGA development debugging of internal FPGA event nodes and data paths. These new features required new custom software, written by BML in .NET for Windows. The software was functional, but graphically slow and was mostly used for trigger setup and then exporting captured data as VCD files into GTKwave for viewing. SUMP1 also did not scale in width, depth or time, it was fixed at 16 events, 2 DWORDs and a 2^20 timestamp ( 1 Million Samples ) both in hardware and software. In 2016 BML decided to do a complete start-over on the SUMP RLE concept and developed SUMP2-RLE ( or just SUMP2 for short ). New Hardware, New Software. More features, better scaling – introducing SUMP2:

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The sump2.v verilog file is designed to work inside any FPGA or ASIC containing block RAM and scales in complexity from 1-4 bytes of events ( 8-32 triggerable and RLE compressible signals ) and 0-16 DWORDs of up to 512 non-compressed data bits. Depth and width of RAM scales on instantiation to best fit a wide range of FPGA technology. The full featured SUMP2 configuration is designed to be used on internal nodes within very large $100 – $1000 FPGAs. In this configuration for analyzing internal FPGA nodes it is very similar to proprietary FPGA vendor solutions such as Xilinx ChipScope and Altera SignalTap. SUMP2 has the advantage of being fully open and also offers RLE compression that can offer 10x – 1000x the time storage of similar FPGA logic analyzers not aided by hardware compression. Duty cycle hardware applications such a pulse-echo radar can readily achieve 5,000x compression using the new RLE engine with 2^32 timestamps. The scalability of SUMP2 also permits it to work in ultra low cost ( sub $5 ) FPGAs such as the Lattice iCE family. The Lattice iCEstick eval board at only $22 with included FTDI USB interface and PROM programming provides for a perfect SUMP2 platform for electronic debugging of Arduino and Raspberry Pi like projects involving 3V serial ports and GPIO. Communication between hardware and software over USB is all done using the Mesa Bus Protocol , an open serial protocol for transferring 32bit PCI reads and writes over UART, SPI and SERDES serial links between computers and FPGAs.

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To fit within the iCE40HX1K FPGA, sump2.v verilog RTL design is instantiated for 16 input events, no DWORDs and 1k depth of RLE capture RAM sampling at 96 MHz. The graphical backend software is sump2.py, a PyGame application used for arming the hardware and dumping and displaying the capture for analysis. Compared to the SUMP1 .NET app, the PyGame SUMP2 version is very fast. Although sump2.py supports exporting and importing VCD files, it is entirely not necessary to use a standalone VCD viewer such as GTKwave or Modelsim.

A simple example of a Unit Under Test.  Below pictured is a 10 MHz ( 100ns period ) oscillator driving a 74ACT161 4bit counter with a 74HC08 AND gate on the d(2) and d(3) upper bits of the counter. A push button switch to ground with a 10K pullup resets the counter. 8 nodes of interest are connected via Dupont ribbon cable to the iCEstick PMOD header.

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Short demonstration video of the sump2.py PyGame application:

The initial full capture of the reset button being released. The capture represents 4168 samples at 96 MHz using only 1K of RAM by utilizing RLE compression. RAM is hard partitioned 50/50 pre and post trigger.sump2_0003.png

SUMP2 has the ability of masking input events prior to arming which allows for greater RLE time compression. By double-clicking and “Hiding” the clk_10m signal prior to a new acquisition, the highly active clock signal is masked. This next capture without the 10 MHz clock is twice the length, or 83uS.  Also notice the very short reset switch bounce captured. Masking the LSB counter bits would further increase total capture time.

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Mouse scroll wheel can be used for zooming in and out in time, allowing for rapid detailed analysis and cursor measurements.

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Right-Clicking the mouse launches popup menus for tool selection.

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The left side popup allows for selecting a signal and then assigning it as a rising or falling edge trigger.

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Steps for building your own open-source SUMP2 Logic Analyzer for the Lattice iCEstick.

What is needed:

  1. $22 iCEstick from Mouser, Digikey or direct from Lattice. ( ICE40HX1K-STICK-EVN )
  2. Free FPGA Diamond Programmer software from Lattice.
  3. Windows Device Driver for the FT2232H USB chip from FTDI ( this may also be included with Lattice Programmer ).

and this free stuff from Black Mesa Labs:

  1. Bitfile for SUMP2 for the Lattice iCE40HX1K FPGA.
  2. bd_server.py – a Python TCP server for communicating to hardware over USB.
  3. sump2.py – a Python PyGame application. Handles triggers and waveform viewing.
  4. FPGA Design Files ( Optional, only needed if not using prebuilt Bitfile ).
  5. 5V Input shield PCB design in CopperConnection ( Optional ).

And finally, a bunch of text file documentation from Black Mesa Labs:

  1. Installation Instructions
  2. FAQ
  3. Program Launching instructions
  4. Troubleshooting guide
  5. Pinout for connecting flying leads to iCEstick
  6. Change Log for Software and Hardware
  7. Bug Report

EE Times Article by Clive “Max” Maxfield on SUMP2

Hackaday Article by Jenny List

Please enjoy SUMP2, a 96 MSPS 16bit 3V logic analyzer for only $22. Follow BML on Twitter for updates on SUMP2 and other open-source software and hardware projects from Black Mesa Labs.

EOF

SUMP2 – 96 MSPS Logic Analyzer for $22