BML DVI digital video for FPGAs over PMOD


2018.11.18 : Update – new board added. Does full 24bit color video using DDR instead of SDR.  Board fab may be purchased from OSH-Park here.


2017.12.15 :  Black Mesa Labs is proud to present two open-source-hardware DVI  video boards for adding TMDS digital video to FPGA platforms with standard PMOD connectors.  These two boards are currently available to purchase as bare fabs directly from OSH-Park, or Gerbers and design files may be downloaded from BML here.


BML 3bit DVI over single-PMOD:


The BML 3bit DVI over single-PMOD uses 7 of 8 available LVCMOS 3.3 pins on a single PMOD to provide 3bit color ( R,G,B 100% On or Off ). Example Verilog design drives 800×600 using a 40 MHz dot clock. The TI TFP410 is very versatile in the resolutions it can generate and is really just limited by the clock that the FPGA can provide and the data rates the PMOD connectors are capable of. The bare 2-layer fab may be purchased from OSH-Park directly for $5 USD ( for 3 boards ) from this link. The TFP410 is about $8 USD. The IC and this HDMI Connector is pretty much the BOM, so the entire cost to assemble is less than $20 USD. The rest of the BOM is Qty-2 0603 0.1uF Caps ( 25V 20% X7Rs were used ), Qty-1 0603 10uF Cap, Qty-1 0805 500ohm 1% resistor and an optional 0805 Ferrite Bead ( 240-2390-1-ND was used, but may be replaced with a wire ).  If you don’t want to power the TFP410 from your FPGA’s 3V rail, the Ferrite Bead may be removed and a BU33 ( or equivalent 5SSOP) 3.3V LDO regulator and 10uF cap may be stuffed and the board may be powered by a 5V input via.

The 3bit color Test Pattern from the board driven by FPGA sample design looks like this:IMG_2530.JPG

Note that blue exists, it is just off screen.  With 3bits of color you get 8 colors by additive color mixing  for Black, White, Red, Green, Blue,  Yellow, Cyan, Magenta.

Below is a picture of the 3b board plugged into a Lattice ICE40 icoBoard which is available from Trenz here.  The smaller iceZero board (PiZero dimensions), also a Lattice ICE40 is a joint BML and Trenz design and would also be a good platform for DVI video and is available here.


Design files for the board, including Gerbers, BOM and text netlist description may be downloaded from my public Dropbox here.


BML 12bit DVI over dual-PMOD:

The BML 12bit DVI over dual-PMOD uses 16 of 16 available LVCMOS 3.3 pins on two PMODs spaced 0.900″ center-to-center per Digilent spec. The 12bit color provides 16 shades each for Red, Green and Blue. Example Verilog design drives 800×600 using a 40 MHz dot clock.  The bare 2-layer fab may be purchased from OSH-Park directly for $11 USD ( for 3 boards ) from this link. BOM is identical to the 3b version, just another PMOD 2×6 right-angle 0.100″ female connector is added. Test Pattern video from the board looks like this ( blue is off screen ):


Example Verilog.  The open-source example Verilog here was used to generate the test patterns shown from a Xilinx Spartan3 board. The design itself is very portable and only requires the FPGA to have a 40 MHz clock and the ability to mirror the clock out to the TFP410 IC using a ODDR or equivalent DDR clock mirroring and the IO ring.  If IO timing for your particular FPGA board doesn’t work, often it may be tweaked to work by adjusting the drive strength and slew rates of the clock out relative to the data out.  Note: BML deliberately chose NOT to use the built-in DDR capability of the TFP410 due to wide variability of I/O timing from various FPGA boards over PMOD interfaces.  SDR is most likely to work across platforms so it was chosen.

A word about video timing – it is tricky. The TFP410 will generate just about any timing you throw at it, but your monitor ( or TV ) might not like it. This on-line calculator is extremely helpful in calculating all the Sync Widths, Front Porch, Back Porch timing parameters. Provided with a resolution ( 800×600 for example ) it will spit out the Verilog def_h_total and def_v_total times ( 1000×667 at 40 MHz for 60 Hz for example ) and the blanking times ( Hsync and Vsync widths, 56 and 3 for example for def_h_sync, def_v_sync ). The porch numbers are then whatever is left over. For example 1000-800-56 = 144. 144/2 = 72 which should work for def_h_fp ( Front Porch ) and def_h_bp ( Back Porch ). It takes patience and experimentation to generate something your monitor is happy with. If your display locks, but isn’t centered, then your porch numbers need to be adjusted accordingly.


BML hopes that you enjoy these free and open-source board designs for adding DVI video to FPGAs. Check back soon for posting on new USB 3.0 to PMOD adapter using FTDI FT600 FIFO Chip.

2017.12.19 : Updated to fix Gerbers for 3b version with incorrect soldermask on video connector.


BML DVI digital video for FPGAs over PMOD

16 thoughts on “BML DVI digital video for FPGAs over PMOD

    1. For assembly of the TQFP chip, I’d recommend a 10x/30x microscope, good soldering station ( not a $20 iron ), decent solder, solder wick and most important liquid solder flux.
      For “programming”, if you don’t already know digital logic design in VHDL or Verilog, it’s a pretty steep learning curve. I’d recommend a good starter CPLD or FPGA board from like Digilent and a good book in FPGA design. I can’t vouch for this book, but something like this


    1. Hi, I am very sorry about that. I corrected that mistake, but OSH-Park has a software bug and doesn’t allow deleting shared projects. Can you point me to where you got the link to the old design? Here is corrected design. . Also, a little bit of sand paper ( fine ) works well for removing the solder mask. This has happened to me before – and hopefully for the last time.


  1. John says:

    Hi, can you help me please. Can you Logic analyser be connected to a PLC via an ethernet port and start charting the PLC logic? (by PLC, I mean a Siemens, Mitsubishi, Allen Bradly or anything else that is out there).


    1. SUMP2 is really designed for short bursts of high speed data ( for example, 100uS of 100 MHz samples ). Regarding PLCs, you are probably needing a deep sample device with lower sample rates. I suggest units. They stream to PC memory ( so Gigabytes of storage versus Kilobytes ).


  2. Hello Kevin,

    Thanks once again for a great PCB! I’m pretty sure I manage to soldered it right, but I’m having a little difficulties finding information on this:

    > The design itself is very portable and only requires the FPGA to have a 40 MHz clock and the ability to mirror the clock out to the TFP410 IC using a ODDR or equivalent DDR clock mirroring and the IO ring.

    … in the context of ICE40 FPGA’s. Could you please give a little example, e.g. for icoBoard or iceZero?


      1. I’m afraid provided example can’t be compiled by IceStorm. It doesn’t know what to do with FDDRCPE and BUFG modules. If I just do:

        // BUFG u0_clk_tree …
        assign clk_40m_tree = clk_40m;
        // FDDRCPE u1_FDDRCPE …
        assign vga_ck = clk_40m_tree;
        … the display says that there is a signal and TFP410 gets a bit warmer so it’s probably doing something. However everything is black no matter what I try.

        Here is the complete code I’m trying to run it on IceStick using only 3 pins for R, G and B. All other pins are connected to ground since they are not pulled down on PCB. Also I noticed that 3V3 pins of left PMOD and right PMOD are not connected so I connected them using a jumper wire. Also it’s worth noting that I didn’t forget to configure PLL, checked all connections and tried to change RGB pins a few times.

        Currently I ran out of ideas. A little piece of advice would be much appreciated!


      2. Hi Kevin! Turned out the problem was with my poor skill of soldering SMD components. I tried to press TFP410 with my finger very hard and everything worked. Thanks for your help and once again thank you for sharing this PCB 🙂

        Liked by 1 person

  3. Tomas Ponzi says:

    Hi Kevin,
    I saw a post from you from 2015 showing the EVEyVideo board and some experiments the FT81X chip and the TFP410. I now must do some similar development for a SBC.
    Do you have EVEyVideo PCB bare board or assembled that you would be willing to sell me?
    Tomas (If you reply please do to


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