IceZero FPGA Board for RaspPi

ice_zero_with_pi_zero.jpeg

2017.02.07 : BML has been very much enchanted with the Lattice FPGA boards for Raspberry Pi, IcoBoard , BlackIce and IceHat. The IceZero board is a BML creation that attempts to combine the best features of all 3 boards into a single design. Hackaday article here.

[ IceZero Block Diagram ]

bml_icezero_block_diagram.png

[ IceZero features common with other designs ]

  1. Fully Open-Source Hardware and Software Design.
  2. Lattice ICE40HX4K FPGA that supports Clifford Wolf’s Project IceStorm tool chain.
  3. Interfaces to Raspberry Pi 2×20 GPIO Header for both power and bus interfaces.
  4. PROM programmable directly from Rasp Pi, no JTAG programmer required.
  5. External SRAM, supporting soft CPU core designs ( code execution ).
  6. Extra large SPI PROM, supporting soft CPU core designs ( code storage ).
  7. Industry standard PMOD expansion headers

[ IceZero features that are BML specific ]

  1. Mesa Bus Protocol 32 MHz SPI link between CPU and FPGA.
  2. 2-Layer PCB design. Orderable via OSH-Park or Gerbers for Downloading.
  3. FTDI 1×6 USB Serial Cable header for use with PC instead of Pi ( or as a soft CPU debug Trace Port ).
  4. Single Pi UART plumbed to FPGA for muxing to multiple external serial devices.

[ Board Design ]:

Please see the IceZero Hardware Design Document and check back for updates.

kevins_art.png

IceZero is drawn as a 2-layer PCB using CopperConnection from RobotRoom, an excellent PCB drawing tool. Board dimension are 2.57×1.18 inches (65.20×30.02mm) , or the near equivalent outline of a Raspberry Pi Zero.

Top:

Top side contains FPGA, SPI PROM, 3 LDOs ( 3.3V, 3.3V, 1.2V ) a OK LED, misc passives and optional 0.100″ PMOD connectors ( 2×6 and 1×6 ) and a single 1×6 0.100″ FTDI header.

bml_ice_zero_front.png

Bottom:

Bottom side contains 100 MHz MEMs oscillator, 256Kx16 SRAM and misc passives.

bml_ice_zero_back.png

[ Bill of Materials ]

Qty-1 : 220-1572-ND : ICE40HX4K-TQ144 : IC FPGA 107 I/O 144TQFP : $5.77
Qty-1 : 706-1306-1-ND : IS61LV25616AL-10TL-TR : IC SRAM 4MBIT 10NS 44TSOP : $3.36
Qty-1 : 1473-1484-1-ND : SIT8008BI-12-XXE-100.000000G : OSC MEMS 100.0000MHZ LVCMOS SMD : $1.23
Qty-1 : 557-1562-ND : N25Q128A13ESE40E : IC FLASH 128MBIT 108MHZ 8SO : $1.82
Qty-2 : BU33TD3WGCT-ND : BU33TD3WG-TR : IC REG LDO 3.3V 0.2A 5SSOP : $0.28
Qty-1 : BU12TD3WGCT-ND : BU12TD3WG-TR : IC REG LDO 1.2V 0.2A 5SSOP : $0.28
Qty-10 : 1276-5086-1-ND : RC1608J103CS : RES SMD 10K OHM 5% 1/10W 0603 : $0.01
Qty-1 : 1276-5062-1-ND : RC1608J102CS : RES SMD 1K OHM 5% 1/10W 0603 : $0.01
Qty-4 : 1276-2087-1-ND : CL10B475KQ8NQNC : CAP CER 4.7UF 6.3V X7R 0603 : $0.03
Qty-16 : 490-9730-1-ND : GRM188R70J104KA01D : CAP CER 0.1UF 6.3V X7R 0603 : $0.03
Qty-1 : 641-1332-1-ND : CDBU0520 : DIODE SCHOTTKY 20V 500MA 0603 : $0.22
Qty-1 : 160-1176-1-ND : LTST-C170CKT : LED RED CLEAR 0805 SMD : $0.15

Optional:
Qty-1 : 2×20 0.100″ Straight Female Connector ( PI GPIO )
Qty-2 : 2×6 0.100″ Straight or Right Angle Female Connector (PMOD)
Qty-2 : 1×6 0.100″ Straight or Right Angle Female Connector (PMOD)
Qty-1 : 1×6 0.100″ Straight or Right Angle Male Connector (FTDI)

WARNING : The Micron 128Mb SPI PROM is end-of-lifing from DigiKey, so future builds will use a different PROM. Considering switching to Micron 64Mb N25Q064A13ESE40F or Cypress 64Mb S25FL164K0XMFI010 for cost and availability reasons. FPGA itself only requires 1Mb, everything above that is useful for soft CPU development for code storage. 64Mb at $0.85 is nice compromise.

[ Ordering IceZero ]

badge-5b7ec47045b78aef6eb9d83b3bac6b1920de805e9a0c227658eac6e19a045b9c.png

bml_ice_zero_osh_park.png

Right now, ordering bare PCB fabs is the only method for getting an IceZero board. Click on this link for ordering Qty-3 PCBs for $15  from OSH-Park. If there is interest, I will send Gerbers out for fab in China and could PayPal sell and ship single bare PCBs within the U.S. for maybe $5 – TBD. You may also optionally download the OSH Gerbers or CopperConnection layout files. All files are provided complete AS-IS and are provided under the CERN Open Hardware Licence.

[ IceZero License Statement ]

This project is licensed with the CERN Open Hardware Licence v1.2. You may redistribute and modify this project under the terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
This project is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.2 for applicable Conditions.

[ FPGA Programming ]

The Python script ice_zero_prog.py may be used for downloading a Lattice PROM file into the SPI PROM from a Raspberry Pi.  This PROM utility is available on GitHub.

[ SUMP2 Sample Design ]

A SUMP2 Verilog sample design for the IceZero is available on my Dropbox. This uses the same Pi software as SUMP2 for IcoBoard.  A very important feature of the IceZero sample design is that it may be used with zero FPGA experience as both a Logic Analyzer and a generic GPIO port expander, providing 24 software defined pins for things like reading switching, driving LEDs and even PWM outputs for servo control.
sump2_on_ice_zero.jpeg

[EOF]

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IceZero FPGA Board for RaspPi

39 thoughts on “IceZero FPGA Board for RaspPi

  1. peek says:

    Hi,
    Thanks a lot for this project, I have purchased 3 pcb and I can’t wait to test them.
    I have just a question, I live in France and the costs of shipping of Digikey are expensive, so I think of placing order to Mouser and there is not N25Q128A13ESE40E in stock.
    Do you think I could replace this reference by the S25FL127SABMFV101 ?

    Thanks by advance for your reply.
    Best regards.

    Like

    1. That part looks fine. I need to pick a new PROM for the BOM. I chose the Micron 128Mbit just to grab the largest density that Lattice JTAG programmer supported. Now that I am writing PROM myself from ice_zero_prog.py, I can use whatever device I like so long as the readback is standard protocol ( should be ). I am considering this 64Mbit Cypress device as it is only $0.85 S25FL164K0XMFI010. The FPGA itself only required 1Mbit, the extra space is for people wanting to do soft CPU core development for code storage.

      Like

  2. If I disconnect a IceZero from the host Pi, are there any limitations on the pins in the 2×20 header? Besides voltage and ground, do they just run directly into the ICE40HX4K? I assume the 17 GPIO are free, but wonder about 11 more pins from SPI and I2C and serial.

    Like

    1. Nice Work! Good example of how the 2×20 header may be soldered topside and have the Pi-Zero on top, with IceZero on bottom ( this doesn’t work with regular Pies since the header is pre-installed ).

      Like

  3. Yeah we are building 3 of them since oshpark does pcbs in batches of 3. I might make the other 2 different. This build was for a colleague at work who had male pins on his Pi zero. I will make mine compatible with the Pi3 and get a Pi Zero to match.

    Like

  4. James says:

    Hey anywhere we can get a prefab for this?

    I would like to test.. but I’d really like to just get stuck in to programming without having to order parts and do the solder.

    If the full fab kit isn’t available would anyone be willing to fabricate and sell a few to me?

    I live in Melbourne, Australia.

    Like

  5. Bo S says:

    I built an IceZero during winter, but the project has been dormant for a while,
    Had some problems with the bitbanged SPI interface to the flash chip, which did not work for me, so i soldered wires from the RPI SPI interface and use spidev interface for programming the flash instead

    Restarted it this week and tried the IceZero Raspberry “Servo Example” bitfile, and my icezero showed signs of working.
    Tried a generated bitfile from own verilog code and yosys, which did not work when i downloaded it to the flash on the IceZero
    The differences turned out to be a 79 byte header in the bit-file for the SPI-flash, adding 79 zero bytes to the beginning of the bitfile, and reflashing made the FPGA work!!

    Liked by 1 person

    1. I built mine but I put the header connector on wrong orientation (so pins 1 and 2 from the board were going to 39 40 on the Pi zero) and connected it briefly to the pi. I desoldered the connector (was a real pain and I had to snip off most of it because desoldering 40 pins is a pain). Now, I need to clean it up and put in a new connector. I hope I didn’t zap anything.

      Like

  6. Jan Rinze says:

    Can the icezero board be programmed using a icoUSBaseboard?
    I have both icoboard and icezero but did not yet try out the latter on the icoUSBaseboard.
    Don’t want to venture in breaking the icezero board at first usel

    Like

    1. Are you assembling this board from the original BML Gerber design, or is this an assembled version from Trenz? The oscillator should definitely output 100 MHz if the correct device is installed. Maybe put an O-Scope on the 3V rail and make sure there aren’t supply problems. A missing bulk cap ( 4.7 uF ) could definitely result in your power rail oscillating at a strange frequency.

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      1. Original design. My colleague soldered the board. Now, I can’t tell where the four 4.7uF and the 16 0.1uF are located? Its hard to tell from the board layout without a schematic. Perhaps he swapped one of the caps since they all are the same size. I will attempt to measure them with the power off.

        Like

    1. Strange. If the rails look okay, next step would be to confirm the oscillator is working stand-alone – a bit of a pain – requiring hot-air to remove I’m afraid. One other possibility is that your PROM contents ( blank presumably ) is configuring the FPGA and the FPGA is driving out the CK net. Easy enough to check by holding off configuration. The RST and SS nets going to the RaspPi connector can be tied to GND I believe and that should hold off configuration.

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  7. okay I am getting a 100 MHz (messed around with the solder pads and reheating and adding more solder to the OSC part) on the CK in center but the CK pin on the pi header is a square wave much slower than the 100 MHz (around .7.86 MHz). Is that right? Are they the same signal?

    Like

  8. Oh – that is correct. The “CK” pin on the Pi Header is for the FPGA configuration via the SPI PROM. This is generated by an oscillator internal to the FPGA and is completely unrelated to the external 100 MHz oscillator. When the Pi programs the PROM, it bit bangs a clock on this “CK” pin to the SPI PROM.

    Like

  9. John says:

    I built a board from the gerber files here and was able to load a test bin that comes with icezprog, but I am a little lost on how to get sump2 working. Can I use the files from AppData.tgz from the icoboard page or do I have to build the project from the dropbox link here? I do not have iCEcube2 and am not sure how if possible to build the project with the IceStorm tools. Any assistance would be appreciated.

    Like

    1. The RaspPi software for the icoboard build is 100% the same as for the IceZero. The only difference you need to worry about is the top_bitmap.bin file for the FPGA itself. So use BOTH the links referenced here. “A SUMP2 Verilog sample design for the IceZero is available on my Dropbox. This uses the same Pi software as SUMP2 for IcoBoard. ” Grab the FPGA firmware from one ( and load the prom with it ) and grab the software from the IcoBoard project.

      Like

      1. John says:

        Ok, I was able to load the firmware and start sump2.py. If I start SUMP2 without the SUMP2 firmware, it correctly reports that it cannot find the hardware and if I have the firmware loaded it proceeds in non demo mode. Running ico_gpio.py returns
        00000001
        00000002
        ffffffff
        5856b8bd
        2016-12-18 11:26:37
        READ 11223344
        READ 00000100
        READ 5856B8BD
        so I am inclined to think that the FPGA is running and has a working SRAM, ROM and oscillator (my soldering job didn’t leave me with much confidence in that). Is that a safe assumption? Next I plan to learn the interface well enough to see if I actually have this working correctly. Thank you for the assistance.

        Like

  10. Congrats! Your FPGA is definitely alive. “11223344” is like an ID register, “00000100” looks like the Version and “5856B8BD” looks like the UNIX timestamp of when I ran synthesis on the build. Looks like you’re off to the races. Make sure and check with my Github website for updates to sump2.py. You should just copy these directly over to your Pi on top of the existing sump2.py. I’ve made a lot of performance and VCD changes recently.

    Like

  11. Puneet says:

    I am sorry. Looks like the board available on Trenz is also compatible with RaspPI. Can you please let me know how this board is difference from the one available on Trenz?
    Will I be able to run your github examples using the board available with Trenz Electronic?

    Like

    1. Yes, my examples will absolutely work with the Trenz iteration of IceZero. The difference between the boards is the BML is a 2-layer PCB with 2 full 2×6 PMODs and 2 half 1×6 PMODs. The Trenz design uses a surface mount 2×20 Pi connector which bought some more space, plus is 6-layer PCB ( if I remember correctly ) and has 4 full 2×6 PMODs. It comes fully assembled and tested of course – which is a huge bonus. I bought 2 myself to ensure full compatibility with my example designs. https://shop.trenz-electronic.de/en/TE0876-02-Ice-Zero-with-Lattice-ICE-ICE40HX

      Like

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