IceZero FPGA Board for RaspPi

ice_zero_with_pi_zero.jpeg

2017.02.07 : BML has been very much enchanted with the Lattice FPGA boards for Raspberry Pi, IcoBoard , BlackIce and IceHat. The IceZero board is a BML creation that attempts to combine the best features of all 3 boards into a single design. Hackaday article here.

[ IceZero Block Diagram ]

bml_icezero_block_diagram.png

[ IceZero features common with other designs ]

  1. Fully Open-Source Hardware and Software Design.
  2. Lattice ICE40HX4K FPGA that supports Clifford Wolf’s Project IceStorm tool chain.
  3. Interfaces to Raspberry Pi 2×20 GPIO Header for both power and bus interfaces.
  4. PROM programmable directly from Rasp Pi, no JTAG programmer required.
  5. External SRAM, supporting soft CPU core designs ( code execution ).
  6. Extra large SPI PROM, supporting soft CPU core designs ( code storage ).
  7. Industry standard PMOD expansion headers

[ IceZero features that are BML specific ]

  1. Mesa Bus Protocol 32 MHz SPI link between CPU and FPGA.
  2. 2-Layer PCB design. Orderable via OSH-Park or Gerbers for Downloading.
  3. FTDI 1×6 USB Serial Cable header for use with PC instead of Pi ( or as a soft CPU debug Trace Port ).
  4. Single Pi UART plumbed to FPGA for muxing to multiple external serial devices.

[ Board Design ]:

Please see the IceZero Hardware Design Document and check back for updates.

kevins_art.png

IceZero is drawn as a 2-layer PCB using CopperConnection from RobotRoom, an excellent PCB drawing tool. Board dimension are 2.57×1.18 inches (65.20×30.02mm) , or the near equivalent outline of a Raspberry Pi Zero.

Top:

Top side contains FPGA, SPI PROM, 3 LDOs ( 3.3V, 3.3V, 1.2V ) a OK LED, misc passives and optional 0.100″ PMOD connectors ( 2×6 and 1×6 ) and a single 1×6 0.100″ FTDI header.

bml_ice_zero_front.png

Bottom:

Bottom side contains 100 MHz MEMs oscillator, 256Kx16 SRAM and misc passives.

bml_ice_zero_back.png

[ Bill of Materials ]

Qty-1 : 220-1572-ND : ICE40HX4K-TQ144 : IC FPGA 107 I/O 144TQFP : $5.77
Qty-1 : 706-1306-1-ND : IS61LV25616AL-10TL-TR : IC SRAM 4MBIT 10NS 44TSOP : $3.36
Qty-1 : 1473-1484-1-ND : SIT8008BI-12-XXE-100.000000G : OSC MEMS 100.0000MHZ LVCMOS SMD : $1.23
Qty-1 : 557-1562-ND : N25Q128A13ESE40E : IC FLASH 128MBIT 108MHZ 8SO : $1.82
Qty-2 : BU33TD3WGCT-ND : BU33TD3WG-TR : IC REG LDO 3.3V 0.2A 5SSOP : $0.28
Qty-1 : BU12TD3WGCT-ND : BU12TD3WG-TR : IC REG LDO 1.2V 0.2A 5SSOP : $0.28
Qty-10 : 1276-5086-1-ND : RC1608J103CS : RES SMD 10K OHM 5% 1/10W 0603 : $0.01
Qty-1 : 1276-5062-1-ND : RC1608J102CS : RES SMD 1K OHM 5% 1/10W 0603 : $0.01
Qty-4 : 1276-2087-1-ND : CL10B475KQ8NQNC : CAP CER 4.7UF 6.3V X7R 0603 : $0.03
Qty-16 : 490-9730-1-ND : GRM188R70J104KA01D : CAP CER 0.1UF 6.3V X7R 0603 : $0.03
Qty-1 : 641-1332-1-ND : CDBU0520 : DIODE SCHOTTKY 20V 500MA 0603 : $0.22
Qty-1 : 160-1176-1-ND : LTST-C170CKT : LED RED CLEAR 0805 SMD : $0.15

Optional:
Qty-1 : 2×20 0.100″ Straight Female Connector ( PI GPIO )
Qty-2 : 2×6 0.100″ Straight or Right Angle Female Connector (PMOD)
Qty-2 : 1×6 0.100″ Straight or Right Angle Female Connector (PMOD)
Qty-1 : 1×6 0.100″ Straight or Right Angle Male Connector (FTDI)

WARNING : The Micron 128Mb SPI PROM is end-of-lifing from DigiKey, so future builds will use a different PROM. Considering switching to Micron 64Mb N25Q064A13ESE40F or Cypress 64Mb S25FL164K0XMFI010 for cost and availability reasons. FPGA itself only requires 1Mb, everything above that is useful for soft CPU development for code storage. 64Mb at $0.85 is nice compromise.

[ Ordering IceZero ]

badge-5b7ec47045b78aef6eb9d83b3bac6b1920de805e9a0c227658eac6e19a045b9c.png

bml_ice_zero_osh_park.png

Right now, ordering bare PCB fabs is the only method for getting an IceZero board. Click on this link for ordering Qty-3 PCBs for $15  from OSH-Park. If there is interest, I will send Gerbers out for fab in China and could PayPal sell and ship single bare PCBs within the U.S. for maybe $5 – TBD. You may also optionally download the OSH Gerbers or CopperConnection layout files. All files are provided complete AS-IS and are provided under the CERN Open Hardware Licence.

[ IceZero License Statement ]

This project is licensed with the CERN Open Hardware Licence v1.2. You may redistribute and modify this project under the terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
This project is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.2 for applicable Conditions.

[ FPGA Programming ]

The Python script ice_zero_prog.py may be used for downloading a Lattice PROM file into the SPI PROM from a Raspberry Pi.  This PROM utility is available on GitHub.

[ SUMP2 Sample Design ]

A SUMP2 Verilog sample design for the IceZero is available on my Dropbox. This uses the same Pi software as SUMP2 for IcoBoard.  A very important feature of the IceZero sample design is that it may be used with zero FPGA experience as both a Logic Analyzer and a generic GPIO port expander, providing 24 software defined pins for things like reading switching, driving LEDs and even PWM outputs for servo control.
sump2_on_ice_zero.jpeg

[EOF]

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IceZero FPGA Board for RaspPi

14 thoughts on “IceZero FPGA Board for RaspPi

  1. peek says:

    Hi,
    Thanks a lot for this project, I have purchased 3 pcb and I can’t wait to test them.
    I have just a question, I live in France and the costs of shipping of Digikey are expensive, so I think of placing order to Mouser and there is not N25Q128A13ESE40E in stock.
    Do you think I could replace this reference by the S25FL127SABMFV101 ?

    Thanks by advance for your reply.
    Best regards.

    Like

    1. That part looks fine. I need to pick a new PROM for the BOM. I chose the Micron 128Mbit just to grab the largest density that Lattice JTAG programmer supported. Now that I am writing PROM myself from ice_zero_prog.py, I can use whatever device I like so long as the readback is standard protocol ( should be ). I am considering this 64Mbit Cypress device as it is only $0.85 S25FL164K0XMFI010. The FPGA itself only required 1Mbit, the extra space is for people wanting to do soft CPU core development for code storage.

      Like

  2. If I disconnect a IceZero from the host Pi, are there any limitations on the pins in the 2×20 header? Besides voltage and ground, do they just run directly into the ICE40HX4K? I assume the 17 GPIO are free, but wonder about 11 more pins from SPI and I2C and serial.

    Like

    1. Nice Work! Good example of how the 2×20 header may be soldered topside and have the Pi-Zero on top, with IceZero on bottom ( this doesn’t work with regular Pies since the header is pre-installed ).

      Like

  3. Yeah we are building 3 of them since oshpark does pcbs in batches of 3. I might make the other 2 different. This build was for a colleague at work who had male pins on his Pi zero. I will make mine compatible with the Pi3 and get a Pi Zero to match.

    Like

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