BML FPGA Design Tutorial Part-3ofN

2024.05.19 : I’m Kevin Hubbard, electronics enthusiast who happens to be an Electrical Engineer. In Part-2 of this tutorial I showed how to implement a VERY simple FPGA design of a 4-tap shift-register using a low-level Verilog netlist to instantiate FPGA gate primitives. In Part-3 I will implement the same design using RTL in both Verilog and VHDL HDLs. The entire series “BML FPGA Design Tutorial” begins here.

Structural netlists are ugly. There – I said it. They are hard to write and even harder to read. They are meant for machines, not humans. I can see above that there are four flip-flops in the design (FDSE and FDRE). That said, looking at the schematic is SO much easier to understand. Schematics are horrible though as they take forever to draw and they don’t scale to millions of flip-flops. There must be a better way. And there is – it’s called RTL !

With RTL you can write in a higher level of Verilog ( or VHDL ) which infers the logic elements. Compare the two 100% functionally equivalent flip-flop implementations.

In both cases, the net u0_q will get the binary state of net u3_q on any clk_100m_tree clock edge where the net pulse_1hz is 1. They’re equivalent. Which is easier to read though? Synthesis makes RTL possible. With the magic of Synthesis, a digital logic design can be designed in RTL with very little knowledge of the gate level primitives of the target device. Synthesis automagically infers the FDSE D Flip-Flop given the RTL higher level description of the design.

It gets better though. The original structure design had to instantiate 4 flops with 4 lines of Verilog. With RTL, that can be done in a single line.

The entire original design implemented in RTL suddenly becomes very human readable. Almost enjoyable in fact :

The VHDL design for the same circuit is nearly equivalent:

So what is the difference between VHDL and Verilog RTL? Honestly – very little. VHDL is a strongly typed language where is Verilog is more loose and wild. What does this mean exactly? VHDL takes twice as much typing to accomplish the same results as Verilog. That said, with Verilog, if you don’t know what you’re doing it’s very easy to make mistakes that go unchecked by Synthesis. I like to think I know what I am doing and definitely prefer Verilog.

Back to the 4-tap shift register design, using the Vivado command “write_verilog” – you can have the tool output a IEEE 1364-2001 compliant Verilog HDL file that contains netlist information generated from the input RTL design files. To keep things simple, I removed the pulse_1hz circuit and left only the 4-tap shift register in the design ( running at 100 MHz instead of 1 Hz ). What should be immediately apparent is that the output netlist below from Vivado looks 99% the same as my original Verilog netlist design from Part-2. Everything that I inferred in my high-level RTL design ( IBUFs, OBUFs, BUFGs, FDREs ) all got instantiated by Vivado. Cool huh? What’s also apparent is that FPGAs aren’t magic microcontrollers. They are giant arrays of D Flip-Flops ( and some other stuff to be covered later ).

That’s the end of Part-3 of this tutorial. In Part-4 I explain the magic of FPGA LUTs in implementing combinatorial logic to make fancy things like counters.

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